Commit d76be73268 for qemu.org
commit d76be73268b212541cba8c7cc8c6882217458d2a
Author: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Date: Tue Sep 29 21:24:18 2026 +0000
tests/tcg/mipsel: add dsp tests
Most of tests have unused or unused but set variables. Instead of fixing
all of them, simply silentify those (unconsequential) warnings.
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Acked-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Tested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Link: https://lore.kernel.org/qemu-devel/20260929212439.110454-4-pierrick.bouvier@oss.qualcomm.com
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
diff --git a/meson_options.txt b/meson_options.txt
index 6c2de6296f..e6dd64b5a8 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -437,6 +437,10 @@ option('tcg_tests_cross_cc_mips', type: 'string',
description: 'cc for mips tcg tests')
option('tcg_tests_cross_cflags_mips', type: 'string',
description: 'cflags for mips tcg tests')
+option('tcg_tests_cross_cc_mipsel', type: 'string',
+ description: 'cc for mipsel tcg tests')
+option('tcg_tests_cross_cflags_mipsel', type: 'string',
+ description: 'cflags for mipsel tcg tests')
option('tcg_tests_cross_cc_mips64', type: 'string',
description: 'cc for mips64 tcg tests')
option('tcg_tests_cross_cflags_mips64', type: 'string',
diff --git a/scripts/meson-buildoptions.sh b/scripts/meson-buildoptions.sh
index 08c9fbb62c..b46005ee96 100644
--- a/scripts/meson-buildoptions.sh
+++ b/scripts/meson-buildoptions.sh
@@ -540,6 +540,7 @@ _meson_option_parse() {
--tcg-tests-cross-cc-mips=*) quote_sh "-Dtcg_tests_cross_cc_mips=$2" ;;
--tcg-tests-cross-cc-mips64=*) quote_sh "-Dtcg_tests_cross_cc_mips64=$2" ;;
--tcg-tests-cross-cc-mips64el=*) quote_sh "-Dtcg_tests_cross_cc_mips64el=$2" ;;
+ --tcg-tests-cross-cc-mipsel=*) quote_sh "-Dtcg_tests_cross_cc_mipsel=$2" ;;
--tcg-tests-cross-cc-or1k=*) quote_sh "-Dtcg_tests_cross_cc_or1k=$2" ;;
--tcg-tests-cross-cc-ppc64=*) quote_sh "-Dtcg_tests_cross_cc_ppc64=$2" ;;
--tcg-tests-cross-cc-ppc64le=*) quote_sh "-Dtcg_tests_cross_cc_ppc64le=$2" ;;
@@ -562,6 +563,7 @@ _meson_option_parse() {
--tcg-tests-cross-cflags-mips=*) quote_sh "-Dtcg_tests_cross_cflags_mips=$2" ;;
--tcg-tests-cross-cflags-mips64=*) quote_sh "-Dtcg_tests_cross_cflags_mips64=$2" ;;
--tcg-tests-cross-cflags-mips64el=*) quote_sh "-Dtcg_tests_cross_cflags_mips64el=$2" ;;
+ --tcg-tests-cross-cflags-mipsel=*) quote_sh "-Dtcg_tests_cross_cflags_mipsel=$2" ;;
--tcg-tests-cross-cflags-or1k=*) quote_sh "-Dtcg_tests_cross_cflags_or1k=$2" ;;
--tcg-tests-cross-cflags-ppc64=*) quote_sh "-Dtcg_tests_cross_cflags_ppc64=$2" ;;
--tcg-tests-cross-cflags-ppc64le=*) quote_sh "-Dtcg_tests_cross_cflags_ppc64le=$2" ;;
diff --git a/tests/tcg/meson.build b/tests/tcg/meson.build
index 96d5d1249f..4c0e30756d 100644
--- a/tests/tcg/meson.build
+++ b/tests/tcg/meson.build
@@ -180,6 +180,7 @@ subdir('i386')
subdir('loongarch64')
subdir('m68k')
subdir('mips')
+subdir('mipsel')
subdir('mips64')
subdir('mips64el')
subdir('or1k')
diff --git a/tests/tcg/mipsel/Makefile b/tests/tcg/mipsel/Makefile
deleted file mode 100644
index 5c6da96870..0000000000
--- a/tests/tcg/mipsel/Makefile
+++ /dev/null
@@ -1,184 +0,0 @@
--include ../../../../config-host.mak
-
-CROSS=mips64el-unknown-linux-gnu-
-
-SIM=qemu-mipsel
-SIM_FLAGS=-cpu 74Kf
-
-CC = $(CROSS)gcc
-CFLAGS = -EL -mabi=32 -march=mips32r2 -mgp32 -mdsp -mdspr2 -static
-
-TESTCASES = test_dsp_r1_absq_s_ph.tst
-TESTCASES += test_dsp_r1_absq_s_w.tst
-TESTCASES += test_dsp_r1_addq_ph.tst
-TESTCASES += test_dsp_r1_addq_s_ph.tst
-TESTCASES += test_dsp_r1_addq_s_w.tst
-TESTCASES += test_dsp_r1_addsc.tst
-TESTCASES += test_dsp_r1_addu_qb.tst
-TESTCASES += test_dsp_r1_addu_s_qb.tst
-TESTCASES += test_dsp_r1_addwc.tst
-TESTCASES += test_dsp_r1_bitrev.tst
-TESTCASES += test_dsp_r1_bposge32.tst
-TESTCASES += test_dsp_r1_cmp_eq_ph.tst
-TESTCASES += test_dsp_r1_cmpgu_eq_qb.tst
-TESTCASES += test_dsp_r1_cmpgu_le_qb.tst
-TESTCASES += test_dsp_r1_cmpgu_lt_qb.tst
-TESTCASES += test_dsp_r1_cmp_le_ph.tst
-TESTCASES += test_dsp_r1_cmp_lt_ph.tst
-TESTCASES += test_dsp_r1_cmpu_eq_qb.tst
-TESTCASES += test_dsp_r1_cmpu_le_qb.tst
-TESTCASES += test_dsp_r1_cmpu_lt_qb.tst
-TESTCASES += test_dsp_r1_dpaq_sa_l_w.tst
-TESTCASES += test_dsp_r1_dpaq_s_w_ph.tst
-TESTCASES += test_dsp_r1_dpau_h_qbl.tst
-TESTCASES += test_dsp_r1_dpau_h_qbr.tst
-TESTCASES += test_dsp_r1_dpsq_sa_l_w.tst
-TESTCASES += test_dsp_r1_dpsq_s_w_ph.tst
-TESTCASES += test_dsp_r1_dpsu_h_qbl.tst
-TESTCASES += test_dsp_r1_dpsu_h_qbr.tst
-TESTCASES += test_dsp_r1_extp.tst
-TESTCASES += test_dsp_r1_extpdp.tst
-TESTCASES += test_dsp_r1_extpdpv.tst
-TESTCASES += test_dsp_r1_extpv.tst
-TESTCASES += test_dsp_r1_extr_rs_w.tst
-TESTCASES += test_dsp_r1_extr_r_w.tst
-TESTCASES += test_dsp_r1_extr_s_h.tst
-TESTCASES += test_dsp_r1_extrv_rs_w.tst
-TESTCASES += test_dsp_r1_extrv_r_w.tst
-TESTCASES += test_dsp_r1_extrv_s_h.tst
-TESTCASES += test_dsp_r1_extrv_w.tst
-TESTCASES += test_dsp_r1_extr_w.tst
-TESTCASES += test_dsp_r1_insv.tst
-TESTCASES += test_dsp_r1_lbux.tst
-TESTCASES += test_dsp_r1_lhx.tst
-TESTCASES += test_dsp_r1_lwx.tst
-TESTCASES += test_dsp_r1_madd.tst
-TESTCASES += test_dsp_r1_maddu.tst
-TESTCASES += test_dsp_r1_maq_sa_w_phl.tst
-TESTCASES += test_dsp_r1_maq_sa_w_phr.tst
-TESTCASES += test_dsp_r1_maq_s_w_phl.tst
-TESTCASES += test_dsp_r1_maq_s_w_phr.tst
-TESTCASES += test_dsp_r1_mfhi.tst
-TESTCASES += test_dsp_r1_mflo.tst
-TESTCASES += test_dsp_r1_modsub.tst
-TESTCASES += test_dsp_r1_msub.tst
-TESTCASES += test_dsp_r1_msubu.tst
-TESTCASES += test_dsp_r1_mthi.tst
-TESTCASES += test_dsp_r1_mthlip.tst
-TESTCASES += test_dsp_r1_mtlo.tst
-TESTCASES += test_dsp_r1_muleq_s_w_phl.tst
-TESTCASES += test_dsp_r1_muleq_s_w_phr.tst
-TESTCASES += test_dsp_r1_muleu_s_ph_qbl.tst
-TESTCASES += test_dsp_r1_muleu_s_ph_qbr.tst
-TESTCASES += test_dsp_r1_mulq_rs_ph.tst
-TESTCASES += test_dsp_r1_mult.tst
-TESTCASES += test_dsp_r1_multu.tst
-TESTCASES += test_dsp_r1_packrl_ph.tst
-TESTCASES += test_dsp_r1_pick_ph.tst
-TESTCASES += test_dsp_r1_pick_qb.tst
-TESTCASES += test_dsp_r1_precequ_ph_qbla.tst
-TESTCASES += test_dsp_r1_precequ_ph_qbl.tst
-TESTCASES += test_dsp_r1_precequ_ph_qbra.tst
-TESTCASES += test_dsp_r1_precequ_ph_qbr.tst
-TESTCASES += test_dsp_r1_preceq_w_phl.tst
-TESTCASES += test_dsp_r1_preceq_w_phr.tst
-TESTCASES += test_dsp_r1_preceu_ph_qbla.tst
-TESTCASES += test_dsp_r1_preceu_ph_qbl.tst
-TESTCASES += test_dsp_r1_preceu_ph_qbra.tst
-TESTCASES += test_dsp_r1_preceu_ph_qbr.tst
-TESTCASES += test_dsp_r1_precrq_ph_w.tst
-TESTCASES += test_dsp_r1_precrq_qb_ph.tst
-TESTCASES += test_dsp_r1_precrq_rs_ph_w.tst
-TESTCASES += test_dsp_r1_precrqu_s_qb_ph.tst
-TESTCASES += test_dsp_r1_raddu_w_qb.tst
-TESTCASES += test_dsp_r1_rddsp.tst
-TESTCASES += test_dsp_r1_repl_ph.tst
-TESTCASES += test_dsp_r1_repl_qb.tst
-TESTCASES += test_dsp_r1_replv_ph.tst
-TESTCASES += test_dsp_r1_replv_qb.tst
-TESTCASES += test_dsp_r1_shilo.tst
-TESTCASES += test_dsp_r1_shilov.tst
-TESTCASES += test_dsp_r1_shll_ph.tst
-TESTCASES += test_dsp_r1_shll_qb.tst
-TESTCASES += test_dsp_r1_shll_s_ph.tst
-TESTCASES += test_dsp_r1_shll_s_w.tst
-TESTCASES += test_dsp_r1_shllv_ph.tst
-TESTCASES += test_dsp_r1_shllv_qb.tst
-TESTCASES += test_dsp_r1_shllv_s_ph.tst
-TESTCASES += test_dsp_r1_shllv_s_w.tst
-TESTCASES += test_dsp_r1_shra_ph.tst
-TESTCASES += test_dsp_r1_shra_r_ph.tst
-TESTCASES += test_dsp_r1_shra_r_w.tst
-TESTCASES += test_dsp_r1_shrav_ph.tst
-TESTCASES += test_dsp_r1_shrav_r_ph.tst
-TESTCASES += test_dsp_r1_shrav_r_w.tst
-TESTCASES += test_dsp_r1_shrl_qb.tst
-TESTCASES += test_dsp_r1_shrlv_qb.tst
-TESTCASES += test_dsp_r1_subq_ph.tst
-TESTCASES += test_dsp_r1_subq_s_ph.tst
-TESTCASES += test_dsp_r1_subq_s_w.tst
-TESTCASES += test_dsp_r1_subu_qb.tst
-TESTCASES += test_dsp_r1_subu_s_qb.tst
-TESTCASES += test_dsp_r1_wrdsp.tst
-TESTCASES += test_dsp_r2_absq_s_qb.tst
-TESTCASES += test_dsp_r2_addqh_ph.tst
-TESTCASES += test_dsp_r2_addqh_r_ph.tst
-TESTCASES += test_dsp_r2_addqh_r_w.tst
-TESTCASES += test_dsp_r2_addqh_w.tst
-TESTCASES += test_dsp_r2_adduh_qb.tst
-TESTCASES += test_dsp_r2_adduh_r_qb.tst
-TESTCASES += test_dsp_r2_addu_ph.tst
-TESTCASES += test_dsp_r2_addu_s_ph.tst
-TESTCASES += test_dsp_r2_append.tst
-TESTCASES += test_dsp_r2_balign.tst
-TESTCASES += test_dsp_r2_cmpgdu_eq_qb.tst
-TESTCASES += test_dsp_r2_cmpgdu_le_qb.tst
-TESTCASES += test_dsp_r2_cmpgdu_lt_qb.tst
-TESTCASES += test_dsp_r2_dpaqx_sa_w_ph.tst
-TESTCASES += test_dsp_r2_dpa_w_ph.tst
-TESTCASES += test_dsp_r2_dpax_w_ph.tst
-TESTCASES += test_dsp_r2_dpaqx_s_w_ph.tst
-TESTCASES += test_dsp_r2_dpsqx_sa_w_ph.tst
-TESTCASES += test_dsp_r2_dpsqx_s_w_ph.tst
-TESTCASES += test_dsp_r2_dps_w_ph.tst
-TESTCASES += test_dsp_r2_dpsx_w_ph.tst
-TESTCASES += test_dsp_r2_mul_ph.tst
-TESTCASES += test_dsp_r2_mulq_rs_w.tst
-TESTCASES += test_dsp_r2_mulq_s_ph.tst
-TESTCASES += test_dsp_r2_mulq_s_w.tst
-TESTCASES += test_dsp_r2_mulsaq_s_w_ph.tst
-TESTCASES += test_dsp_r2_mulsa_w_ph.tst
-TESTCASES += test_dsp_r2_mul_s_ph.tst
-TESTCASES += test_dsp_r2_precr_qb_ph.tst
-TESTCASES += test_dsp_r2_precr_sra_ph_w.tst
-TESTCASES += test_dsp_r2_precr_sra_r_ph_w.tst
-TESTCASES += test_dsp_r2_prepend.tst
-TESTCASES += test_dsp_r2_shra_qb.tst
-TESTCASES += test_dsp_r2_shra_r_qb.tst
-TESTCASES += test_dsp_r2_shrav_qb.tst
-TESTCASES += test_dsp_r2_shrav_r_qb.tst
-TESTCASES += test_dsp_r2_shrl_ph.tst
-TESTCASES += test_dsp_r2_shrlv_ph.tst
-TESTCASES += test_dsp_r2_subqh_ph.tst
-TESTCASES += test_dsp_r2_subqh_r_ph.tst
-TESTCASES += test_dsp_r2_subqh_r_w.tst
-TESTCASES += test_dsp_r2_subqh_w.tst
-TESTCASES += test_dsp_r2_subuh_qb.tst
-TESTCASES += test_dsp_r2_subuh_r_qb.tst
-TESTCASES += test_dsp_r2_subu_ph.tst
-TESTCASES += test_dsp_r2_subu_s_ph.tst
-
-
-all: $(TESTCASES)
-
-%.tst: %.c
- $(CC) $(CFLAGS) $< -o $@
-
-check: $(TESTCASES)
- @for case in $(TESTCASES); do \
- echo $(SIM) $(SIM_FLAGS) ./$$case;\
- $(SIM) $(SIM_FLAGS) ./$$case; \
- done
-
-clean:
- $(RM) -rf $(TESTCASES)
diff --git a/tests/tcg/mipsel/meson.build b/tests/tcg/mipsel/meson.build
new file mode 100644
index 0000000000..0bf7e840a7
--- /dev/null
+++ b/tests/tcg/mipsel/meson.build
@@ -0,0 +1,188 @@
+tests = []
+
+tests_dsp = [
+ 'test_dsp_r1_absq_s_ph.c',
+ 'test_dsp_r1_absq_s_w.c',
+ 'test_dsp_r1_addq_ph.c',
+ 'test_dsp_r1_addq_s_ph.c',
+ 'test_dsp_r1_addq_s_w.c',
+ 'test_dsp_r1_addsc.c',
+ 'test_dsp_r1_addu_qb.c',
+ 'test_dsp_r1_addu_s_qb.c',
+ 'test_dsp_r1_addwc.c',
+ 'test_dsp_r1_bitrev.c',
+ 'test_dsp_r1_bposge32.c',
+ 'test_dsp_r1_cmp_eq_ph.c',
+ 'test_dsp_r1_cmp_le_ph.c',
+ 'test_dsp_r1_cmp_lt_ph.c',
+ 'test_dsp_r1_cmpgu_eq_qb.c',
+ 'test_dsp_r1_cmpgu_le_qb.c',
+ 'test_dsp_r1_cmpgu_lt_qb.c',
+ 'test_dsp_r1_cmpu_eq_qb.c',
+ 'test_dsp_r1_cmpu_le_qb.c',
+ 'test_dsp_r1_cmpu_lt_qb.c',
+ 'test_dsp_r1_dpaq_s_w_ph.c',
+ 'test_dsp_r1_dpaq_sa_l_w.c',
+ 'test_dsp_r1_dpau_h_qbl.c',
+ 'test_dsp_r1_dpau_h_qbr.c',
+ 'test_dsp_r1_dpsq_s_w_ph.c',
+ 'test_dsp_r1_dpsq_sa_l_w.c',
+ 'test_dsp_r1_dpsu_h_qbl.c',
+ 'test_dsp_r1_dpsu_h_qbr.c',
+ 'test_dsp_r1_extp.c',
+ 'test_dsp_r1_extpdp.c',
+ 'test_dsp_r1_extpdpv.c',
+ 'test_dsp_r1_extpv.c',
+ 'test_dsp_r1_extr_r_w.c',
+ 'test_dsp_r1_extr_rs_w.c',
+ 'test_dsp_r1_extr_s_h.c',
+ 'test_dsp_r1_extr_w.c',
+ 'test_dsp_r1_extrv_r_w.c',
+ 'test_dsp_r1_extrv_rs_w.c',
+ 'test_dsp_r1_extrv_s_h.c',
+ 'test_dsp_r1_extrv_w.c',
+ 'test_dsp_r1_insv.c',
+ 'test_dsp_r1_lbux.c',
+ 'test_dsp_r1_lhx.c',
+ 'test_dsp_r1_lwx.c',
+ 'test_dsp_r1_madd.c',
+ 'test_dsp_r1_maddu.c',
+ 'test_dsp_r1_main.c',
+ 'test_dsp_r1_maq_s_w_phl.c',
+ 'test_dsp_r1_maq_s_w_phr.c',
+ 'test_dsp_r1_maq_sa_w_phl.c',
+ 'test_dsp_r1_maq_sa_w_phr.c',
+ 'test_dsp_r1_mfhi.c',
+ 'test_dsp_r1_mflo.c',
+ 'test_dsp_r1_modsub.c',
+ 'test_dsp_r1_msub.c',
+ 'test_dsp_r1_msubu.c',
+ 'test_dsp_r1_mthi.c',
+ 'test_dsp_r1_mthlip.c',
+ 'test_dsp_r1_mtlo.c',
+ 'test_dsp_r1_muleq_s_w_phl.c',
+ 'test_dsp_r1_muleq_s_w_phr.c',
+ 'test_dsp_r1_muleu_s_ph_qbl.c',
+ 'test_dsp_r1_muleu_s_ph_qbr.c',
+ 'test_dsp_r1_mulq_rs_ph.c',
+ 'test_dsp_r1_mult.c',
+ 'test_dsp_r1_multu.c',
+ 'test_dsp_r1_packrl_ph.c',
+ 'test_dsp_r1_pick_ph.c',
+ 'test_dsp_r1_pick_qb.c',
+ 'test_dsp_r1_preceq_w_phl.c',
+ 'test_dsp_r1_preceq_w_phr.c',
+ 'test_dsp_r1_precequ_ph_qbl.c',
+ 'test_dsp_r1_precequ_ph_qbla.c',
+ 'test_dsp_r1_precequ_ph_qbr.c',
+ 'test_dsp_r1_precequ_ph_qbra.c',
+ 'test_dsp_r1_preceu_ph_qbl.c',
+ 'test_dsp_r1_preceu_ph_qbla.c',
+ 'test_dsp_r1_preceu_ph_qbr.c',
+ 'test_dsp_r1_preceu_ph_qbra.c',
+ 'test_dsp_r1_precrq_ph_w.c',
+ 'test_dsp_r1_precrq_qb_ph.c',
+ 'test_dsp_r1_precrq_rs_ph_w.c',
+ 'test_dsp_r1_precrqu_s_qb_ph.c',
+ 'test_dsp_r1_raddu_w_qb.c',
+ 'test_dsp_r1_rddsp.c',
+ 'test_dsp_r1_repl_ph.c',
+ 'test_dsp_r1_repl_qb.c',
+ 'test_dsp_r1_replv_ph.c',
+ 'test_dsp_r1_replv_qb.c',
+ 'test_dsp_r1_shilo.c',
+ 'test_dsp_r1_shilov.c',
+ 'test_dsp_r1_shll_ph.c',
+ 'test_dsp_r1_shll_qb.c',
+ 'test_dsp_r1_shll_s_ph.c',
+ 'test_dsp_r1_shll_s_w.c',
+ 'test_dsp_r1_shllv_ph.c',
+ 'test_dsp_r1_shllv_qb.c',
+ 'test_dsp_r1_shllv_s_ph.c',
+ 'test_dsp_r1_shllv_s_w.c',
+ 'test_dsp_r1_shra_ph.c',
+ 'test_dsp_r1_shra_r_ph.c',
+ 'test_dsp_r1_shra_r_w.c',
+ 'test_dsp_r1_shrav_ph.c',
+ 'test_dsp_r1_shrav_r_ph.c',
+ 'test_dsp_r1_shrav_r_w.c',
+ 'test_dsp_r1_shrl_qb.c',
+ 'test_dsp_r1_shrlv_qb.c',
+ 'test_dsp_r1_subq_ph.c',
+ 'test_dsp_r1_subq_s_ph.c',
+ 'test_dsp_r1_subq_s_w.c',
+ 'test_dsp_r1_subu_qb.c',
+ 'test_dsp_r1_subu_s_qb.c',
+ 'test_dsp_r1_wrdsp.c',
+ 'test_dsp_r2_absq_s_qb.c',
+ 'test_dsp_r2_addqh_ph.c',
+ 'test_dsp_r2_addqh_r_ph.c',
+ 'test_dsp_r2_addqh_r_w.c',
+ 'test_dsp_r2_addqh_w.c',
+ 'test_dsp_r2_addu_ph.c',
+ 'test_dsp_r2_addu_s_ph.c',
+ 'test_dsp_r2_adduh_qb.c',
+ 'test_dsp_r2_adduh_r_qb.c',
+ 'test_dsp_r2_append.c',
+ 'test_dsp_r2_balign.c',
+ 'test_dsp_r2_cmpgdu_eq_qb.c',
+ 'test_dsp_r2_cmpgdu_le_qb.c',
+ 'test_dsp_r2_cmpgdu_lt_qb.c',
+ 'test_dsp_r2_dpa_w_ph.c',
+ 'test_dsp_r2_dpaqx_s_w_ph.c',
+ 'test_dsp_r2_dpaqx_sa_w_ph.c',
+ 'test_dsp_r2_dpax_w_ph.c',
+ 'test_dsp_r2_dps_w_ph.c',
+ 'test_dsp_r2_dpsqx_s_w_ph.c',
+ 'test_dsp_r2_dpsqx_sa_w_ph.c',
+ 'test_dsp_r2_dpsx_w_ph.c',
+ 'test_dsp_r2_mul_ph.c',
+ 'test_dsp_r2_mul_s_ph.c',
+ 'test_dsp_r2_mulq_rs_w.c',
+ 'test_dsp_r2_mulq_s_ph.c',
+ 'test_dsp_r2_mulq_s_w.c',
+ 'test_dsp_r2_mulsa_w_ph.c',
+ 'test_dsp_r2_mulsaq_s_w_ph.c',
+ 'test_dsp_r2_precr_qb_ph.c',
+ 'test_dsp_r2_precr_sra_ph_w.c',
+ 'test_dsp_r2_precr_sra_r_ph_w.c',
+ 'test_dsp_r2_prepend.c',
+ 'test_dsp_r2_shra_qb.c',
+ 'test_dsp_r2_shra_r_qb.c',
+ 'test_dsp_r2_shrav_qb.c',
+ 'test_dsp_r2_shrav_r_qb.c',
+ 'test_dsp_r2_shrl_ph.c',
+ 'test_dsp_r2_shrlv_ph.c',
+ 'test_dsp_r2_subqh_ph.c',
+ 'test_dsp_r2_subqh_r_ph.c',
+ 'test_dsp_r2_subqh_r_w.c',
+ 'test_dsp_r2_subqh_w.c',
+ 'test_dsp_r2_subu_ph.c',
+ 'test_dsp_r2_subu_s_ph.c',
+ 'test_dsp_r2_subuh_qb.c',
+ 'test_dsp_r2_subuh_r_qb.c',
+]
+
+foreach src: tests_dsp
+ tests += {
+ src: {
+ 'cflags': ['-EL', '-mabi=32', '-march=mips32r2', '-mgp32', '-mdsp', '-mdspr2',
+ '-Wno-unused-but-set-variable', '-Wno-unused-variable'],
+ 'qemu_args': ['-cpu', '74Kf'],
+ }
+ }
+endforeach
+
+if 'qemu-mipsel' in emulators
+ tcg_tests += {
+ 'mipsel-linux-user': {
+ 'cc': 'mipsel-linux-gnu-gcc',
+ 'cc_dockerfile': 'debian-all-test-cross',
+ 'cc_feat_cflags': cc_feat_cflags,
+ 'folder': 'mipsel',
+ 'gdb_arch': 'mipsel',
+ 'qemu': emulators['qemu-mipsel'],
+ 'tests': tests,
+ }
+ }
+endif