Commit e766674577 for qemu.org

commit e7666745773fb6680e46f716335e18dc5102fe32
Author: Ferdinand Schober <schober@cs.fau.de>
Date:   Mon Nov 9 13:52:08 2026 +0000

    arm/cpu: fix GIC v3 flag for a64fx

    The a64fx CPU model wrongfully set GIC bits in the
    processor feature register (ID_AA64PFR0).

    I traced this back to e31c70ac04001df5e540b79843834277e283fa71,
    where A64FX got added.

    This bit is supposed to get set conditionally in id_aa64pfr0_read,
    depending on whether or not a gicv3 is present, from what I can tell.
    Qemu picks gic-version=2 by default, while v3 gets advertised due to this flag.
    Recent EDK2 firmware accesses ICC_SRE_EL2 in this case and crashes.

    Clear the GIC field, as the other CPU models do.

    Cc: qemu-stable@nongnu.org
    Fixes: e31c70ac0400 ("target-arm: Add support for Fujitsu A64FX")
    Signed-off-by: Ferdinand Schober <schober@cs.fau.de>
    Message-id: 20261103145254.1543907-1-schober@cs.fau.de
    Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index a6352e6307..e46cdd3167 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -505,7 +505,8 @@ static void aarch64_a64fx_initfn(Object *obj)
     SET_IDREG(isar, REVIDR, 0);
     cpu->ctr = 0x86668006;
     cpu->reset_sctlr = 0x30000180;
-    SET_IDREG(isar, ID_AA64PFR0, 0x0000000101111111); /* No RAS Extensions */
+    /* No RAS Extensions, GIC filled in later */
+    SET_IDREG(isar, ID_AA64PFR0, 0x0000000100111111);
     SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000000);
     SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408);
     SET_IDREG(isar, ID_AA64DFR1, 0x0000000000000000);