Commit eccd982eb5 for qemu.org

commit eccd982eb52f6dd5467dabeb6a096d067ccda545
Author: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Date:   Sat Oct 24 06:16:07 2026 +0000

    target-info: add target_base_riscv

    Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
    Acked-by: Alistair Francis <alistair.francis@wdc.com>
    Link: https://lore.kernel.org/qemu-devel/20261024061616.27381-2-pierrick.bouvier@oss.qualcomm.com
    Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>

diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h
index 923c00c917..2cd4cc5671 100644
--- a/include/qemu/target-info.h
+++ b/include/qemu/target-info.h
@@ -120,6 +120,13 @@ bool target_ppc64(void);
  */
 bool target_s390x(void);

+/**
+ * target_base_riscv:
+ *
+ * Returns whether the target architecture is RISC-V 32-bit or 64-bit.
+ */
+bool target_base_riscv(void);
+
 /**
  * target_riscv64:
  *
diff --git a/target-info.c b/target-info.c
index b8a4a7ebf7..e67d7bed52 100644
--- a/target-info.c
+++ b/target-info.c
@@ -110,6 +110,17 @@ bool target_s390x(void)
     return target_arch() == SYS_EMU_TARGET_S390X;
 }

+bool target_base_riscv(void)
+{
+    switch (target_arch()) {
+    case SYS_EMU_TARGET_RISCV32:
+    case SYS_EMU_TARGET_RISCV64:
+        return true;
+    default:
+        return false;
+    }
+}
+
 bool target_riscv64(void)
 {
     return target_arch() == SYS_EMU_TARGET_RISCV64;