Commit ee23f530e9 for qemu.org

commit ee23f530e99d1091f31585dd0ca1b948d4873939
Author: Rick Richard <rick@sloservers.com>
Date:   Mon Oct 5 03:40:07 2026 -0700

    hw/riscv/virt-acpi-build: Fix the UART register width in SPCR

    The riscv virt board uses a 16550 UART with an 8-bit register stride,
    but the SPCR table reports 32, which looks to have been copied from
    arm virt, whose PL011 has a 32-bit stride.  Change it to the correct
    stride for a 16550.

    Fixes: 3e6f1e61b4 ("hw/riscv/virt-acpi-build.c: Generate SPCR table")
    Signed-off-by: Rick Richard <rick@sloservers.com>
    Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
    Message-ID: <20261005104008.214588-3-rick@sloservers.com>
    Cc: qemu-stable@nongnu.org
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 8e516ec114..0475dcb5c6 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -246,7 +246,7 @@ spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s)
     AcpiSpcrData serial = {
         .interface_type = 0x12,       /* 16550 compatible */
         .base_addr.id = AML_AS_SYSTEM_MEMORY,
-        .base_addr.width = 32,
+        .base_addr.width = 8,
         .base_addr.offset = 0,
         .base_addr.size = 1,
         .base_addr.addr = s->memmap[VIRT_UART0].base,