Commit f0fc86dd93 for qemu.org
commit f0fc86dd93ceb053706b5b46240f0b7a9f1eccd1
Author: Anton Johansson <anjo@rev.ng>
Date: Fri Sep 18 00:04:59 2026 +0200
target/riscv: Stub out kvm functions
Functions used externally by hw/riscv are stubbed out for non-kvm
configurations, allowing a single compilation of hw/riscv.
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260918-hw-riscv-cpu-int-v5-5-f98c5a244636@rev.ng>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
diff --git a/target/riscv/kvm/kvm-stub.c b/target/riscv/kvm/kvm-stub.c
new file mode 100644
index 0000000000..64e39c96d8
--- /dev/null
+++ b/target/riscv/kvm/kvm-stub.c
@@ -0,0 +1,23 @@
+/*
+ * QEMU RISCV specific KVM stubs
+ *
+ * Copyright (c) rev.ng Labs Srl.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "target/riscv/kvm/kvm_riscv.h"
+
+void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
+ uint64_t aia_irq_num, uint64_t aia_msi_num,
+ uint64_t aplic_base, uint64_t imsic_base,
+ uint64_t guest_num)
+{
+ g_assert_not_reached();
+}
+
+uint64_t kvm_riscv_get_timebase_frequency(RISCVCPU *cpu)
+{
+ g_assert_not_reached();
+}
diff --git a/target/riscv/kvm/meson.build b/target/riscv/kvm/meson.build
index 7e92415091..75e35b2150 100644
--- a/target/riscv/kvm/meson.build
+++ b/target/riscv/kvm/meson.build
@@ -1 +1,2 @@
riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm-cpu.c'))
+riscv_stubs_ss.add(files('kvm-stub.c'))
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 42d0f6d538..e1b51d2bd4 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -19,6 +19,8 @@ riscv_ss.add(files(
'gdbstub.c',
))
+riscv_stubs_ss = ss.source_set()
+
riscv_system_ss = ss.source_set()
riscv_system_ss.add(files(
'arch_dump.c',
@@ -33,3 +35,4 @@ subdir('kvm')
target_arch += {'riscv': riscv_ss}
target_system_arch += {'riscv': riscv_system_ss}
+target_stubs_arch += {'riscv': riscv_stubs_ss}