Commit 03de3e44a706 for kernel

commit 03de3e44a706cd96f75ede209cb289324367ed4b
Merge: cd80afff4877 5efaf92da436
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Sun Dec 28 09:44:26 2025 -0800

    Merge tag 'riscv-for-linus-6.19-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

    Pull RISC-V updates from Paul Walmsley:
     "Nothing exotic here; these are the cleanup and new ISA extension
      probing patches (not including CFI):

       - Add probing and userspace reporting support for the standard RISC-V
         ISA extensions Zilsd and Zclsd, which implement load/store dual
         instructions on RV32

       - Abstract the register saving code in setup_sigcontext() so it can
         be used for stateful RISC-V ISA extensions beyond the vector
         extension

       - Add the SBI extension ID and some initial data structure
         definitions for the RISC-V standard SBI debug trigger extension

       - Clean up some code slightly: change some page table functions to
         avoid atomic operations oinn !SMP and to avoid unnecessary casts to
         atomic_long_t; and use the existing RISCV_FULL_BARRIER macro in
         place of some open-coded 'fence rw,rw' instructions"

    * tag 'riscv-for-linus-6.19-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
      riscv: Add SBI debug trigger extension and function ids
      riscv/atomic.h: use RISCV_FULL_BARRIER in _arch_atomic* function.
      riscv: hwprobe: export Zilsd and Zclsd ISA extensions
      riscv: add ISA extension parsing for Zilsd and Zclsd
      dt-bindings: riscv: add Zilsd and Zclsd extension descriptions
      riscv: mm: use xchg() on non-atomic_long_t variables, not atomic_long_xchg()
      riscv: mm: ptep_get_and_clear(): avoid atomic ops when !CONFIG_SMP
      riscv: mm: pmdp_huge_get_and_clear(): avoid atomic ops when !CONFIG_SMP
      riscv: signal: abstract header saving for setup_sigcontext