Commit 055f9cb47d for qemu.org

commit 055f9cb47d4e1c5889bdbca4e6dc1d5201964ccb
Author: Abhigyan Kumar <314abh@gmail.com>
Date:   Thu Jul 30 04:30:28 2026 +0530

    target/riscv: prevent abrupt abortion on unassigned value write to tdata

    tdata_csr_write is approachable by guest programs. In case of unassigned
    values written to a tdata CSR in debug mode, the switch-case falls
    through straight to default causing an immediate abort. The risc-v spec
    says:

        All tdata registers follow write-any-read-legal semantics. If a debugger
        writes an unsupported configuration, the register will read back a value
        that is supported (which may simply be a disabled trigger). This means
        that a debugger must always read back values it writes to tdata
        registers, unless it already knows what is supported.

    This fix correctly ensures that the WARL behaviour of tdata CSRs.

    Fixes: a42bd001 ("target/riscv: debug: Determine the trigger type from
    tdata1.type")
    Signed-off-by: Abhigyan Kumar <314abh@gmail.com>
    Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
    Message-ID: <20260729230028.1797355-1-314abh@gmail.com>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c
index 148201f3cb..e4d719a1da 100644
--- a/target/riscv/tcg/debug.c
+++ b/target/riscv/tcg/debug.c
@@ -951,7 +951,8 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
                       trigger_type);
         break;
     default:
-        g_assert_not_reached();
+        qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d is unassigned\n",
+                trigger_type);
     }
 }