Commit 073e62fd33fe for kernel

commit 073e62fd33fe9cec754cb89e60c0ebbab781a50a
Merge: 73cc4da3857b 8da45c93dfa9
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Thu Aug 20 14:53:54 2026 -0700

    Merge tag 'riscv-for-linus-7.3-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

    Pull RISC-V updates from Paul Walmsley

     - Add initial definitions and discovery for the Smcsrind, Sscsrind,
       Smcntrpmf, Ssccfg, Smcdeleg, Zicclsm, Ziccamoa, Ziccif, Ziccrse,
       Za64rs, and Ssqosid RISC-V ISA extensions

     - Improve the RISC-V update_mmu_cache_range() implementation by using
       flush-by-ASID, enabling performance improvements on
       microarchitectures that support related optimizations; and by taking
       advantage of the Svinval RISC-V ISA extension on microarchitectures
       that support it

     - Shrink CFI shadow stack allocation further (to 512MB) to save virtual
       address space (and physical memory on systems with strict overcommit
       policies)

     - Add initial CPU context switch support for QoS tagging (Ssqosid)

     - Change our vector misaligned access speed test code to be
       synchronous, avoiding a bunch of bugs related to unnecessary
       asynchronicity

     - Enable ARCH_HAS_ACPI_TABLE_UPGRADE for RISC-V to help with ACPI table
       debugging (similar to ARM64 and x86)

     - Extract vDSO section offsets at build time, rather than run time, to
       avoid the boot time overhead

     - Use assembler directives to control the use of instructions from the
       RISC-V ISA extensions Zacas and Zabha, rather than compiler -march
       flags that could affect the whole kernel (similar to ARM64)

     - Add a kselftest for kprobes support for the c.jal instruction on
       RISC-V

     - When UEFI runtime services are available, use them to restart and
       power off

     - Fix ARCH_HAS_ACPI_TABLE_UPGRADE for RISC-V by adding a missing
       include file to the ACPI code

     - Move contiguous DMA memory reservation later in the boot, to ensure
       that the correct global and per-node pools are allocated when
       CONFIG_CMA_SIZE_PERNUMA is enabled

     - Disallow probes on breakpoint handlers to avoid recursing
       indefinitely into do_trap_break()

     - Patch the compat vDSO during runtime alternatives processing, not
       only the standard vDSO

     - Remove some leftover XIP support elements missed by commit
       9b3a2be84803 ("riscv: Remove support for XIP kernel")

     - Fix broadcast timer switching in ACPI LPI power states by
       implementing a RISC-V version of arch_get_idle_state_flags()

     - Miscellaneous fixes, including: vDSO makefile simplification; marking
       our default_power_off() as __noreturn; error path fixes in the PMU
       SBI perf driver; RISC-V extension capitalization consistency; the use
       of BIT() macros in one of our include files; and some documentation
       fixes

    * tag 'riscv-for-linus-7.3-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (39 commits)
      RISC-V: hwprobe: Use BIT macro to avoid warnings
      riscv: alternative: Also patch the compat vDSO
      riscv: alternative: Use the statically extracted vDSO section offsets
      riscv: vdso: Add symbols for the alternative section boundaries
      riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to cpufeature and hwprobe
      riscv: Add Zicclsm to cpufeature and hwprobe
      riscv: cpufeature: Clarify ISA spec version for canonical order
      riscv: Standardize extension capitalization
      riscv: kprobes: Prevent probes in breakpoint handlers
      riscv: cmpxchg: Use .option arch for Zacas and Zabha
      riscv: acpi: Handle LPI architectural context loss flags
      riscv: further remove XIP
      riscv: Add support for srmcfg CSR from Ssqosid extension
      riscv: Detect the Ssqosid extension
      dt-bindings: riscv: Add Ssqosid extension description
      dt-bindings: riscv: add Counter delegation ISA extensions description
      RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing
      RISC-V: Add Ssccfg extension CSR definition
      dt-bindings: riscv: add Smcntrpmf ISA extension description
      RISC-V: Add Smcntrpmf extension parsing
      ...

diff --cc arch/riscv/include/asm/acpi.h
index f598520ac903,980aa11d7741..cdefa1f2d67d
--- a/arch/riscv/include/asm/acpi.h
+++ b/arch/riscv/include/asm/acpi.h
@@@ -67,7 -69,23 +69,24 @@@ int acpi_get_riscv_isa(struct acpi_tabl

  void acpi_get_cbo_block_size(struct acpi_table_header *table, u32 *cbom_size,
  			     u32 *cboz_size, u32 *cbop_size);
 +acpi_handle acpi_get_riscv_gsi_handle(u32 gsi);
+
+ /*
+  * RISC-V Functional Fixed Hardware Specification Version v1.0.1,
+  * Chapter 3.1.2, Table 4: Arch. Context Lost Flags
+  */
+ #define RISCV_LPI_HART_TIMER_CTXT_LOST		BIT(0)
+
+ static inline unsigned int arch_get_idle_state_flags(u32 arch_flags)
+ {
+ 	if (arch_flags & RISCV_LPI_HART_TIMER_CTXT_LOST)
+ 		return CPUIDLE_FLAG_TIMER_STOP;
+
+ 	return 0;
+ }
+
+ #define arch_get_idle_state_flags arch_get_idle_state_flags
+
  #else
  static inline void acpi_init_rintc_map(void) { }
  static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu)