Commit 1c3bc5ea56 for qemu.org
commit 1c3bc5ea569850739c1f963d58defeb94c8f76ce
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: Sat Apr 4 13:13:18 2026 +0200
ati-vga: Fix pitch and offset registers mask
Remove the Radeon specific masks for offset and pitch registers. While
the documentation is not clear about it I believe it is a copy&paste
error from the combined DST_PITCH_OFFSET register that has less bits
so more constrained than the individual registers which should not
have this mask.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-ID: <20260404111318.8334E596A22@zero.eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
diff --git a/hw/display/ati.c b/hw/display/ati.c
index 7bb57c44d9..88a5bbbf07 100644
--- a/hw/display/ati.c
+++ b/hw/display/ati.c
@@ -820,18 +820,12 @@ static void ati_mm_write(void *opaque, hwaddr addr,
ati_cursor_define(s);
break;
case DST_OFFSET:
- if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
s->regs.dst_offset = data & 0xfffffff0;
- } else {
- s->regs.dst_offset = data & 0xfffffc00;
- }
break;
case DST_PITCH:
- if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
s->regs.dst_pitch = data & 0x3fff;
+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
s->regs.dst_tile = (data >> 16) & 1;
- } else {
- s->regs.dst_pitch = data & 0x3ff0;
}
break;
case DST_TILE:
@@ -941,18 +935,12 @@ static void ati_mm_write(void *opaque, hwaddr addr,
s->regs.dst_height = (data >> 16) & 0x3fff;
break;
case SRC_OFFSET:
- if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
s->regs.src_offset = data & 0xfffffff0;
- } else {
- s->regs.src_offset = data & 0xfffffc00;
- }
break;
case SRC_PITCH:
- if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
s->regs.src_pitch = data & 0x3fff;
+ if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
s->regs.src_tile = (data >> 16) & 1;
- } else {
- s->regs.src_pitch = data & 0x3ff0;
}
break;
case DP_BRUSH_BKGD_CLR: