Commit 209c2c9af6 for qemu.org
commit 209c2c9af6259054938ab4c0226e5a41ee92d4ec
Author: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>
Date: Thu Jan 8 13:41:36 2026 +0000
target/riscv: Add cpu_set_exception_base
Add a new function, so we can change reset vector from platforms
during runtime.
Signed-off-by: Chao-ying Fu <cfu@mips.com>
Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20260108134128.2218102-2-djordje.todorovic@htecgroup.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f22b504772..c2222228d5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -73,6 +73,22 @@ bool riscv_cpu_option_set(const char *optname)
return g_hash_table_contains(general_user_opts, optname);
}
+#ifndef CONFIG_USER_ONLY
+/* This is used in runtime only. */
+void cpu_set_exception_base(int vp_index, target_ulong address)
+{
+ RISCVCPU *cpu;
+ CPUState *cs = qemu_get_cpu(vp_index);
+ if (cs == NULL) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "cpu_set_exception_base: invalid vp_index: %u",
+ vp_index);
+ }
+ cpu = RISCV_CPU(cs);
+ cpu->env.resetvec = address;
+}
+#endif
+
static void riscv_cpu_cfg_merge(RISCVCPUConfig *dest, const RISCVCPUConfig *src)
{
#define BOOL_FIELD(x) dest->x |= src->x;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0939e6f08c..08a6e491f3 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -668,6 +668,10 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env,
target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
+#ifndef CONFIG_USER_ONLY
+void cpu_set_exception_base(int vp_index, target_ulong address);
+#endif
+
FIELD(TB_FLAGS, MEM_IDX, 0, 3)
FIELD(TB_FLAGS, FS, 3, 2)
/* Vector flags */