Commit 26f6d70954 for qemu.org

commit 26f6d70954c3c912e2929afaf81bab959435bf92
Author: Anton Blanchard <antonb@tenstorrent.com>
Date:   Sun Jan 4 23:37:24 2026 +0000

    target/riscv: rvv: Allow fractional LMUL on vector SHA instructions

    Vector SHA instructions incorrectly raise an illegal instruction exception
    when LMUL < 1. The ISA only states that LMUL*VLEN >= EGW:

      For element-group instructions, LMUL*VLEN must always be at least as
      large as EGW, otherwise an illegal-instruction exception is raised, even
      if vl=0.

    There is already a check for this:

      MAXSZ(s) >= egw_bytes

    so just remove the check for a fractional LMUL.

    Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
    Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
    Message-ID: <20260104233724.192886-1-antonb@tenstorrent.com>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
index 27bf3f0b68..32255d3aa0 100644
--- a/target/riscv/insn_trans/trans_rvvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvvk.c.inc
@@ -426,8 +426,7 @@ static bool vsha_check(DisasContext *s, arg_rmrr *a)
            vsha_check_sew(s) &&
            MAXSZ(s) >= egw_bytes &&
            !is_overlapped(a->rd, mult, a->rs1, mult) &&
-           !is_overlapped(a->rd, mult, a->rs2, mult) &&
-           s->lmul >= 0;
+           !is_overlapped(a->rd, mult, a->rs2, mult);
 }

 GEN_VV_UNMASKED_TRANS(vsha2ms_vv, vsha_check, ZVKNH_EGS)