Commit 282771e1f9 for qemu.org

commit 282771e1f9b9b6e0147adf5f9d676325175b1767
Merge: 2624b1a767 4d82676cfc
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date:   Wed Apr 29 09:22:50 2026 -0400

    Merge tag 'pull-riscv-to-apply-20260429-1' of https://github.com/alistair23/qemu into staging

    RISC-V PR for 11.1.

    * Use standard EN_PRI bit for PRI IOMMU
    * Add draft RISC-V Zbr ext as xbr0p93
    * Forbid to use legacy native endianness API
    * Fix irq_overflow_left residual value bug in IOMMU
    * Add IPSR.PMIP RW1C support to IOMMU
    * Use kvm timer frequency when kvm enabled
    * Fix stale ptshift and base on page walk restart
    * Fix heap OOB in ACLINT MTIMER multi-socket
    * Reject RISC-V HTIF invalid signature ranges
    * Fix RV32 henvcfg/stateen CSR handling
    * Add Zvfbfa extension support
    * Allow fractional LMUL on vector SHA instructions
    * Add Tenstorrent mvendorid
    * Warn if a ELF format file is loaded as a binary
    * Initialize riscv_excp_names[] and riscv_intr_names[] using designated initializer
    * Mask xepc[0] only when Zc* extension is enabled
    * Generate access fault if sc comparison fails
    * Don't OR mip.SEIP when mvien is one
    * Use ELEN for Fractional LMUL check
    * Fix Zjpm implementation
    * Handle mask/source overlap of vector reduction instructions

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    * tag 'pull-riscv-to-apply-20260429-1' of https://github.com/alistair23/qemu: (51 commits)
      target/riscv: rvv: Handle mask/source overlap of vector reduction instructions
      target/riscv: Fix pointer masking translation mode check bug
      target/riscv: Rename riscv_pm_get_virt_pmm() to riscv_pm_get_vm_ldst_pmm()
      target/riscv: Fix pointer masking for virtual-machine load/store insns
      target/riscv: Fix pointer masking PMM field selection logic
      target/riscv: Add a helper to return the current effective priv mode
      target/riscv: fix address masking
      target/riscv: Use ELEN for Fractional LMUL check
      target/riscv: Don't OR mip.SEIP when mvien is one
      target/riscv: Generate access fault if sc comparison fails
      target/riscv: Mask xepc[0] only when Zc* extension is enabled
      target/riscv: Initialize riscv_excp_names[] and riscv_intr_names[] using designated initializer
      target/riscv: fix RV32 stateen CSR handling
      hw/riscv/boot: Warn if a ELF format file is loaded as a binary
      target/riscv: tt-ascalon: Add Tenstorrent mvendorid
      target/riscv: rvv: Allow fractional LMUL on vector SHA instructions
      target/riscv: Expose Zvfbfa extension as a cpu property
      target/riscv: rvv: Support Zvfbfa vector bf16 operations
      target/riscv: Introduce BF16 canonical NaN for Zvfbfa extension
      target/riscv: Introduce altfmt into DisasContext
      ...

    Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>