Commit 2a9847868f for qemu.org

commit 2a9847868fcf5e93671c4d759db685474d2d7342
Author: Peter Maydell <peter.maydell@linaro.org>
Date:   Mon Jul 20 19:05:29 2026 +0100

    target/arm: GICv5 cpuif: Writes to ICC_APR_EL1 can change IRQ/FIQ

    The ICC_APR_EL1 register values change the current running priority,
    which we use in our calculations in gic_hppi().  Changing them can
    affect whether we have a HPPI, and so the value of the IRQ/FIQ
    outputs.  We need to trigger an update in the register writefn.

    Fixes: 9bd90bddb79 ("target/arm: GICv5 cpuif: Signal IRQ or FIQ")
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
    Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
    Message-id: 20260714091806.3568281-3-peter.maydell@linaro.org

diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c
index 8e2a08fdb6..a6e6c44084 100644
--- a/target/arm/tcg/gicv5-cpuif.c
+++ b/target/arm/tcg/gicv5-cpuif.c
@@ -495,6 +495,7 @@ static void gic_icc_apr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
     GICv5Domain domain = gicv5_logical_domain(env);
     value &= 0xffffffff;
     env->gicv5_cpuif.icc_apr[domain] = value;
+    gicv5_update_irq_fiq(env);
 }

 static uint64_t gic_icc_apr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri)