Commit 2be159078e for qemu.org

commit 2be159078ea26feac4c9c9902acf8906f1a05c2a
Merge: bde2492aac 85d38315fd
Author: Richard Henderson <richard.henderson@linaro.org>
Date:   Sun Aug 23 23:04:09 2026 -0700

    Merge tag 'pull-riscv-to-apply-20260824-1' of https://github.com/alistair23/qemu into staging

    RISC-V PR for 11.1

    * Fix IMSIC CSR write and add tests
    * Parametrise debug trigger number
    * Add 'svbare' satp-mode
    * Fix RINTC PLIC context ID for KVM
    * Avoid abort when reading vtype before env->xl is set
    * Skip reset for KVM irqchip
    * Skip FP/Vector sync on KVM_PUT_RUNTIME_STATE
    * More FDT cleanups (PLIC)
    * Make FCTL.BE in IOMMU read only 0
    * Check DC.TC reserved bits in IOMMU
    * Apply UXL WARL handling to vsstatus
    * Set cmd_ill IOFENCE.C if rsvp bits are set in IOMMU
    * Set RISCV_IOMMU_FQ_HDR_PV appropriately
    * Report QEMU CPU archid as 42
    * Check PMP before updating PTE
    * Add the Tenstorrent Atlantis machine

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    * tag 'pull-riscv-to-apply-20260824-1' of https://github.com/alistair23/qemu: (96 commits)
      target/riscv/tcg: sret in virtual user mode raises virtual instruction exception
      target/riscv: Make Zcmt JVT loads endian-aware
      tests/tcg/riscv64: add misa write test
      riscv: csr: do not drop C bit on misa write
      target/riscv: Allow UXL to be 3 in mstatus on rv128
      target/riscv: Fix sstatus update in rv128
      target/riscv: Restore register dump zero padding
      tests/qtest: remove trace output from k230 watchdog test
      target/riscv: enforce even register constraints for Zdinx fcvt pairs
      target/riscv: reject FMV.X.W/FMV.W.X under Zfinx
      target/riscv: honor zicbo* envcfg gating in linux-user mode
      disas/riscv: Sort riscv-op.c.inc
      disas/riscv: Split rvi_opcode_data
      disas/riscv: Tidy decode of mop.r.n and mop.rr.n
      disas/riscv: Tidy decode of c.mop.n
      disas/riscv: Merge all c.mop.n to one pattern
      disas/riscv: Merge all mop.rr.n to one pattern
      disas/riscv: Merge all mop.r.n to one pattern
      disas/riscv: Split out riscv-op.c.inc
      disas/riscv: Move rv_op_illegal to riscv.c
      ...

    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>