Commit 354c16c69f for qemu.org

commit 354c16c69f371a1e68bc9feb501a6c2a4410944e
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date:   Mon Jun 23 14:21:19 2025 -0300

    target/riscv: print all available CSRs in riscv_cpu_dump_state()

    At this moment we're printing a small selection of CSRs. There's no
    particular reason to not print all of them.

    We're ignoring the note about CSR_SSTATUS being ommited because it can
    be read via CSR_MSTATUS. There's a huge list of CSRs that would fall in
    this category and it would be an extra burden to manage them, not
    mentioning having to document "we're not listing X because it's the same
    value as Y" to users.

    Remove 'dump_csrs' and use the existing 'csr_ops' array to print all
    available CSRs. Create two helpers in csr.c to identify FPU and VPU CSRs
    and skip them - they'll be printed in the FPU/VPU blocks later.

    Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
    Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
    Message-ID: <20250623172119.997166-4-dbarboza@ventanamicro.com>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 063374be62..60abdf3324 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -545,44 +545,27 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 #endif
     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
 #ifndef CONFIG_USER_ONLY
-    {
-        static const int dump_csrs[] = {
-            CSR_MHARTID,
-            CSR_MSTATUS,
-            CSR_MSTATUSH,
-            /*
-             * CSR_SSTATUS is intentionally omitted here as its value
-             * can be figured out by looking at CSR_MSTATUS
-             */
-            CSR_HSTATUS,
-            CSR_VSSTATUS,
-            CSR_MIP,
-            CSR_MIE,
-            CSR_MIDELEG,
-            CSR_HIDELEG,
-            CSR_MEDELEG,
-            CSR_HEDELEG,
-            CSR_MTVEC,
-            CSR_STVEC,
-            CSR_VSTVEC,
-            CSR_MEPC,
-            CSR_SEPC,
-            CSR_VSEPC,
-            CSR_MCAUSE,
-            CSR_SCAUSE,
-            CSR_VSCAUSE,
-            CSR_MTVAL,
-            CSR_STVAL,
-            CSR_HTVAL,
-            CSR_MTVAL2,
-            CSR_MSCRATCH,
-            CSR_SSCRATCH,
-            CSR_SATP,
-        };
+    for (i = 0; i < ARRAY_SIZE(csr_ops); i++) {
+        int csrno = i;

-        for (i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
-            riscv_dump_csr(env, dump_csrs[i], f);
+        /*
+         * Early skip when possible since we're going
+         * through a lot of NULL entries.
+         */
+        if (csr_ops[csrno].predicate == NULL) {
+            continue;
         }
+
+        /*
+         * FPU and VPU CSRs will be printed in the
+         * CPU_DUMP_FPU/CPU_DUMP_VPU blocks later.
+         */
+        if (riscv_csr_is_fpu(csrno) ||
+            riscv_csr_is_vpu(csrno)) {
+            continue;
+        }
+
+        riscv_dump_csr(env, csrno, f);
     }
 #endif

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 90b3e95105..b3c0be5779 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -969,6 +969,8 @@ bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu);

 /* CSR function table */
 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
+bool riscv_csr_is_fpu(int csrno);
+bool riscv_csr_is_vpu(int csrno);

 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[];

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5c91658c3d..a69b9a11ab 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -5802,6 +5802,24 @@ static RISCVException write_jvt(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }

+bool riscv_csr_is_fpu(int csrno)
+{
+    if (!csr_ops[csrno].predicate) {
+        return false;
+    }
+
+    return csr_ops[csrno].predicate == fs;
+}
+
+bool riscv_csr_is_vpu(int csrno)
+{
+    if (!csr_ops[csrno].predicate) {
+        return false;
+    }
+
+    return csr_ops[csrno].predicate == vs;
+}
+
 /*
  * Control and Status Register function table
  * riscv_csr_operations::predicate() must be provided for an implemented CSR