Commit 3632840c3b for qemu.org

commit 3632840c3b335fe728fb934d0e7f58df8d06c3b1
Author: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Date:   Tue Jun 16 17:29:41 2026 +0200

    target/ppc: Restrict TCGTBCPUState to TCG

    TCGTBCPUState is a structure used during TCG translation,
    therefore not needed when TCG is not available.

    Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
    Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
    Message-Id: <20260616153432.92939-4-philmd@oss.qualcomm.com>

diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index a07e6a7b7b..acf74c543a 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -27,7 +27,6 @@
 #include "power8-pmu.h"
 #include "cpu-models.h"
 #include "spr_common.h"
-#include "accel/tcg/cpu-ops.h"
 #include "internal.h"

 /* Swap temporary saved registers with GPRs */
@@ -261,6 +260,7 @@ void hreg_update_pmu_hflags(CPUPPCState *env)
     env->hflags |= hreg_compute_pmu_hflags_value(env);
 }

+#ifdef CONFIG_TCG
 TCGTBCPUState ppc_get_tb_cpu_state(CPUState *cs)
 {
     CPUPPCState *env = cpu_env(cs);
@@ -277,6 +277,7 @@ TCGTBCPUState ppc_get_tb_cpu_state(CPUState *cs)

     return (TCGTBCPUState){ .pc = env->nip, .flags = hflags_current };
 }
+#endif /* CONFIG_TCG */

 #ifndef CONFIG_USER_ONLY
 void cpu_interrupt_exittb(CPUState *cs)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index dda23b6609..a3bb12afd9 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -22,7 +22,6 @@
 #include "exec/memop.h"
 #include "hw/core/registerfields.h"
 #include "exec/page-protection.h"
-#include "accel/tcg/tb-cpu-state.h"

 static inline bool ppc_env_is_little_endian(const CPUPPCState *env)
 {
@@ -326,6 +325,10 @@ static inline int ger_pack_masks(int pmsk, int ymsk, int xmsk)
     return msk;
 }

+#ifdef CONFIG_TCG
+#include "accel/tcg/tb-cpu-state.h"
+
 TCGTBCPUState ppc_get_tb_cpu_state(CPUState *cs);
+#endif

 #endif /* PPC_INTERNAL_H */