Commit 409c7d8682 for qemu.org

commit 409c7d8682ae91c5e275d744d55a2ac19789534a
Author: Joel Stanley <joel@jms.id.au>
Date:   Thu Aug 13 12:54:14 2026 +0930

    target/riscv: Restore register dump zero padding

    The register values lost their leading zeroes when the underlying type
    was changed, resulting in mismatched padding and harder to read output.

    Print with a runtime field width based on MXL, so values are 16 hex
    digits on rv64 and 8 on rv32, matching the csr and fp dump. This avoids
    adding target_ulong back into the dump.

    Fixes: c4e6bc63853c ("target/riscv: Fix size of gpr and gprh")
    Signed-off-by: Joel Stanley <joel@jms.id.au>
    Reviewed-by: Anton Johansson <anjo@rev.ng>
    Reviewed-by: Max Chou <max.chou@sifive.com>
    Message-ID: <20260813032421.54438-1-joel@jms.id.au>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 79ddde419a..a13177b7b7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -651,6 +651,9 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
+    bool rv32 = riscv_cpu_is_32bit(cpu);
+    int width = rv32 ? 8 : 16;
+    uint64_t mask = rv32 ? UINT32_MAX : UINT64_MAX;
     int i, j;
     uint8_t *p;

@@ -665,7 +668,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
         qemu_fprintf(f, " %-13s %d\n", "elp", env->elp);
     }
 #endif
-    qemu_fprintf(f, " %-13s %" PRIx64 "\n", "pc", env->pc);
+    qemu_fprintf(f, " %-13s %0*" PRIx64 "\n", "pc", width, env->pc & mask);
 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
     for (i = 0; i < ARRAY_SIZE(csr_ops); i++) {
         int csrno = i;
@@ -692,8 +695,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 #endif

     for (i = 0; i < 32; i++) {
-        qemu_fprintf(f, " %-8s %" PRIx64,
-                     riscv_int_regnames[i], env->gpr[i]);
+        qemu_fprintf(f, " %-8s %0*" PRIx64,
+                     riscv_int_regnames[i], width, env->gpr[i] & mask);
         if ((i & 3) == 3) {
             qemu_fprintf(f, "\n");
         }