Commit 4d82676cfc for qemu.org

commit 4d82676cfc6e14099d0e529445a5ee520752ebe5
Author: Anton Blanchard <antonb@tenstorrent.com>
Date:   Fri Apr 17 12:06:26 2026 +0000

    target/riscv: rvv: Handle mask/source overlap of vector reduction instructions

    Masked vector reduction instructions must not use v0 as a source register.
    Check rs1 and rs2 against the mask register when vm=0.

    Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
    Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
    Message-ID: <20260417120626.77415-1-antonb@tenstorrent.com>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 5b72926b3c..e65356eb7c 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3265,6 +3265,8 @@ static bool reduction_check(DisasContext *s, arg_rmrr *a)
 {
     return require_rvv(s) &&
            vext_check_isa_ill(s) &&
+           require_vm(a->vm, a->rs1) &&
+           require_vm(a->vm, a->rs2) &&
            vext_check_reduction(s, a->rs2);
 }