Commit 4efed64ffc for qemu.org

commit 4efed64ffcdb99b977ad0b2129a9c0208456a6c9
Author: Peter Maydell <peter.maydell@linaro.org>
Date:   Wed Dec 31 17:08:58 2025 +0000

    target/arm: Rename access_aa64_tid5() to access_tid5()

    There is no equivalent access_aa32_tid5() (HCR_EL2.TID5 only exists
    starting from v8); rename access_aa64_tid5() to access_tid5() to line
    up with the naming we now have for the TID1 and TID3 check functions.

    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
    Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
    Message-id: 20251231170858.254594-5-peter.maydell@linaro.org

diff --git a/target/arm/helper.c b/target/arm/helper.c
index acfb2cbc31..dce648b482 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5429,8 +5429,8 @@ static const ARMCPRegInfo dcpodp_reg[] = {
       .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
 };

-static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInfo *ri,
-                                       bool isread)
+static CPAccessResult access_tid5(CPUARMState *env, const ARMCPRegInfo *ri,
+                                  bool isread)
 {
     if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID5)) {
         return CP_ACCESS_TRAP_EL2;
@@ -7467,7 +7467,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
         ARMCPRegInfo gmid_reginfo = {
             .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
             .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
-            .access = PL1_R, .accessfn = access_aa64_tid5,
+            .access = PL1_R, .accessfn = access_tid5,
             .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize,
         };
         define_one_arm_cp_reg(cpu, &gmid_reginfo);