Commit 51b126d315 for qemu.org
commit 51b126d31586859c12bee76079a82cf80d282385
Author: Brian Cain <brian.cain@oss.qualcomm.com>
Date: Tue Sep 8 21:01:36 2026 -0700
target/hexagon: add v81 interrupt registers
Reviewed-by: Marco Liebel <marco.liebel@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
diff --git a/hw/hexagon/hexagon_globalreg.c b/hw/hexagon/hexagon_globalreg.c
index 61621cf2b8..616cddf304 100644
--- a/hw/hexagon/hexagon_globalreg.c
+++ b/hw/hexagon/hexagon_globalreg.c
@@ -84,6 +84,11 @@ static const char *hex_sreg_names[] = {
[HEX_SREG_S61] = "s61",
[HEX_SREG_S62] = "s62",
[HEX_SREG_S63] = "s63",
+ [HEX_SREG_IPEND] = "ipend",
+ [HEX_SREG_IAD] = "iad",
+ [HEX_SREG_ISDBST1] = "isdbst1",
+ [HEX_SREG_ISDBST2] = "isdbst2",
+ [HEX_SREG_BRKPTINFO1] = "brkptinfo1",
};
static const char *get_sreg_name(uint32_t reg)
@@ -100,6 +105,8 @@ static const uint32_t global_sreg_immut_masks[NUM_SREGS] = {
[HEX_SREG_MODECTL] = IMMUTABLE,
[HEX_SREG_SYSCFG] = 0x80001c00,
[HEX_SREG_IPENDAD] = IMMUTABLE,
+ [HEX_SREG_IPEND] = IMMUTABLE,
+ [HEX_SREG_IAD] = IMMUTABLE,
[HEX_SREG_VID] = 0xfc00fc00,
[HEX_SREG_VID1] = 0xfc00fc00,
[HEX_SREG_BESTWAIT] = 0xfffffe00,
@@ -109,6 +116,9 @@ static const uint32_t global_sreg_immut_masks[NUM_SREGS] = {
[HEX_SREG_DIAG] = 0x00000000,
[HEX_SREG_REV] = IMMUTABLE,
[HEX_SREG_ISDBST] = IMMUTABLE,
+ [HEX_SREG_ISDBST1] = IMMUTABLE,
+ [HEX_SREG_ISDBST2] = IMMUTABLE,
+ [HEX_SREG_BRKPTINFO1] = IMMUTABLE,
[HEX_SREG_ISDBCFG0] = 0xe0000000,
[HEX_SREG_BRKPTPC0] = 0x00000003,
[HEX_SREG_BRKPTCFG0] = 0xfc007000,
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index fb0e3caa48..fad526ccfb 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -103,7 +103,16 @@ const char * const hexagon_sregnames[] = {
"pmucnt5", "pmucnt6", "pmucnt7", "pmucnt0", "pmucnt1",
"pmucnt2", "pmucnt3", "pmuevtcfg", "pmustid0", "pmuevtcfg1",
"pmustid1", "timerlo", "timerhi", "pmucfg", "s59",
- "s60", "s61", "s62", "s63",
+ "s60", "s61", "s62", "s63", "commit1t",
+ "commit2t", "commit3t", "commit4t", "commit5t", "commit6t",
+ "pcycle1t", "pcycle2t", "pcycle3t", "pcycle4t", "pcycle5t",
+ "pcycle6t", "stfinst", "isdbcmd", "isdbver", "brkptinfo",
+ "s80", "commit7t", "commit8t", "pcycle7t", "pcycle8t",
+ "commit9t", "commit10t", "commit11t", "commit12t", "commit13t",
+ "commit14t", "commit15t", "commit16t", "pcycle9t", "pcycle10t",
+ "pcycle11t", "pcycle12t", "pcycle13t", "pcycle14t", "pcycle15t",
+ "pcycle16t", "ipend", "iad", "isdbst1", "isdbst2",
+ "brkptinfo1",
};
G_STATIC_ASSERT(NUM_SREGS == ARRAY_SIZE(hexagon_sregnames));
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 719979d6c3..b1533680bd 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -23,7 +23,7 @@
#ifndef CONFIG_USER_ONLY
#define NUM_GREGS 32
#define GREG_WRITES_MAX 2
-#define NUM_SREGS 64
+#define NUM_SREGS 106
#define SREG_WRITES_MAX 2
#endif
diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c
index 9ce260d744..eea5f60b46 100644
--- a/target/hexagon/cpu_helper.c
+++ b/target/hexagon/cpu_helper.c
@@ -333,10 +333,17 @@ int get_exe_mode(const CPUHexagonState *env)
E_bit = thread_enabled_mask & (0x1 << env->threadId);
thread_wait_mask = GET_FIELD(MODECTL_W, modectl);
W_bit = thread_wait_mask & (0x1 << env->threadId);
- isdbst = cpu->globalregs ?
- hexagon_globalreg_read(cpu->globalregs, HEX_SREG_ISDBST,
- env->threadId) : 0;
- debugmode = GET_FIELD(ISDBST_DEBUGMODE, isdbst);
+ if (cpu->cfg.hex_def->hex_version >= HEX_VER_V81) {
+ isdbst = cpu->globalregs ?
+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_ISDBST2,
+ env->threadId) : 0;
+ debugmode = GET_FIELD(ISDBST2_DEBUGMODE, isdbst);
+ } else {
+ isdbst = cpu->globalregs ?
+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_ISDBST,
+ env->threadId) : 0;
+ debugmode = GET_FIELD(ISDBST_DEBUGMODE, isdbst);
+ }
D_bit = debugmode & (0x1 << env->threadId);
if (!D_bit && !W_bit && !E_bit) {
diff --git a/target/hexagon/hex_interrupts.c b/target/hexagon/hex_interrupts.c
index 2b2834af95..0b714b7383 100644
--- a/target/hexagon/hex_interrupts.c
+++ b/target/hexagon/hex_interrupts.c
@@ -21,7 +21,7 @@ static bool hex_is_qualified_for_int(CPUHexagonState *env, int int_num);
static bool get_syscfg_gie(CPUHexagonState *env)
{
- HexagonCPU *cpu = env_archcpu(env);
+ const HexagonCPU *cpu = env_archcpu(env);
uint32_t syscfg =
hexagon_globalreg_read(cpu->globalregs, HEX_SREG_SYSCFG,
env->threadId);
@@ -52,85 +52,138 @@ static void set_ssr_ex_cause(CPUHexagonState *env, int ex, uint32_t cause)
hexagon_modify_ssr(env, new, old);
}
-static bool get_iad_bit(CPUHexagonState *env, int int_num)
+static bool has_split_ipend_iad(const CPUHexagonState *env)
+{
+ const HexagonCPU *cpu = env_archcpu(env);
+
+ return cpu->cfg.hex_def->hex_version >= HEX_VER_V81;
+}
+
+static uint32_t get_iad(CPUHexagonState *env)
{
HexagonCPU *cpu = env_archcpu(env);
- uint32_t ipendad =
- hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
- env->threadId);
- uint32_t iad = GET_FIELD(IPENDAD_IAD, ipendad);
+
+ if (has_split_ipend_iad(env)) {
+ return hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IAD,
+ env->threadId);
+ }
+ return GET_FIELD(IPENDAD_IAD,
+ hexagon_globalreg_read(cpu->globalregs,
+ HEX_SREG_IPENDAD,
+ env->threadId));
+}
+
+static void set_iad(CPUHexagonState *env, uint32_t iad)
+{
+ HexagonCPU *cpu = env_archcpu(env);
+
+ if (has_split_ipend_iad(env)) {
+ hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IAD, iad,
+ env->threadId);
+ } else {
+ uint32_t ipendad =
+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
+ env->threadId);
+
+ fSET_FIELD(ipendad, IPENDAD_IAD, iad);
+ hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD,
+ ipendad, env->threadId);
+ }
+}
+
+static bool get_iad_bit(CPUHexagonState *env, int int_num)
+{
+ uint32_t iad = get_iad(env);
+
return extract32(iad, int_num, 1);
}
static void set_iad_bit(CPUHexagonState *env, int int_num, int val)
{
- HexagonCPU *cpu = env_archcpu(env);
- uint32_t ipendad =
- hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
- env->threadId);
- uint32_t iad = GET_FIELD(IPENDAD_IAD, ipendad);
+ uint32_t iad = get_iad(env);
+
iad = deposit32(iad, int_num, 1, val);
- fSET_FIELD(ipendad, IPENDAD_IAD, iad);
- hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD,
- ipendad, env->threadId);
+ set_iad(env, iad);
}
static uint32_t get_ipend(CPUHexagonState *env)
{
HexagonCPU *cpu = env_archcpu(env);
- uint32_t ipendad =
- hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
- env->threadId);
- return GET_FIELD(IPENDAD_IPEND, ipendad);
+
+ if (has_split_ipend_iad(env)) {
+ return hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPEND,
+ env->threadId);
+ }
+ return GET_FIELD(IPENDAD_IPEND,
+ hexagon_globalreg_read(cpu->globalregs,
+ HEX_SREG_IPENDAD,
+ env->threadId));
}
static inline bool get_ipend_bit(CPUHexagonState *env, int int_num)
{
- HexagonCPU *cpu = env_archcpu(env);
- uint32_t ipendad =
- hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
- env->threadId);
- uint32_t ipend = GET_FIELD(IPENDAD_IPEND, ipendad);
+ uint32_t ipend = get_ipend(env);
return extract32(ipend, int_num, 1);
}
static void clear_ipend(CPUHexagonState *env, uint32_t mask)
{
HexagonCPU *cpu = env_archcpu(env);
- uint32_t ipendad =
- hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
- env->threadId);
- uint32_t ipend = GET_FIELD(IPENDAD_IPEND, ipendad);
+ uint32_t ipend = get_ipend(env);
+
ipend &= ~mask;
- fSET_FIELD(ipendad, IPENDAD_IPEND, ipend);
- hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD,
- ipendad, env->threadId);
+ if (has_split_ipend_iad(env)) {
+ hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPEND, ipend,
+ env->threadId);
+ } else {
+ uint32_t ipendad =
+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
+ env->threadId);
+
+ fSET_FIELD(ipendad, IPENDAD_IPEND, ipend);
+ hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD,
+ ipendad, env->threadId);
+ }
}
static void set_ipend(CPUHexagonState *env, uint32_t mask)
{
HexagonCPU *cpu = env_archcpu(env);
- uint32_t ipendad =
- hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
- env->threadId);
- uint32_t ipend = GET_FIELD(IPENDAD_IPEND, ipendad);
+ uint32_t ipend = get_ipend(env);
+
ipend |= mask;
- fSET_FIELD(ipendad, IPENDAD_IPEND, ipend);
- hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD,
- ipendad, env->threadId);
+ if (has_split_ipend_iad(env)) {
+ hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPEND, ipend,
+ env->threadId);
+ } else {
+ uint32_t ipendad =
+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
+ env->threadId);
+
+ fSET_FIELD(ipendad, IPENDAD_IPEND, ipend);
+ hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD,
+ ipendad, env->threadId);
+ }
}
static void set_ipend_bit(CPUHexagonState *env, int int_num, int val)
{
HexagonCPU *cpu = env_archcpu(env);
- uint32_t ipendad =
- hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
- env->threadId);
- uint32_t ipend = GET_FIELD(IPENDAD_IPEND, ipendad);
+ uint32_t ipend = get_ipend(env);
+
ipend = deposit32(ipend, int_num, 1, val);
- fSET_FIELD(ipendad, IPENDAD_IPEND, ipend);
- hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD,
- ipendad, env->threadId);
+ if (has_split_ipend_iad(env)) {
+ hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPEND, ipend,
+ env->threadId);
+ } else {
+ uint32_t ipendad =
+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
+ env->threadId);
+
+ fSET_FIELD(ipendad, IPENDAD_IPEND, ipend);
+ hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD,
+ ipendad, env->threadId);
+ }
}
static bool get_imask_bit(CPUHexagonState *env, int int_num)
diff --git a/target/hexagon/hex_regs.h b/target/hexagon/hex_regs.h
index 214b7b8fde..1f6bf9f88a 100644
--- a/target/hexagon/hex_regs.h
+++ b/target/hexagon/hex_regs.h
@@ -195,6 +195,48 @@ enum {
HEX_SREG_S61 = 61,
HEX_SREG_S62 = 62,
HEX_SREG_S63 = 63,
+ HEX_SREG_COMMIT1T = 64,
+ HEX_SREG_COMMIT2T = 65,
+ HEX_SREG_COMMIT3T = 66,
+ HEX_SREG_COMMIT4T = 67,
+ HEX_SREG_COMMIT5T = 68,
+ HEX_SREG_COMMIT6T = 69,
+ HEX_SREG_PCYCLE1T = 70,
+ HEX_SREG_PCYCLE2T = 71,
+ HEX_SREG_PCYCLE3T = 72,
+ HEX_SREG_PCYCLE4T = 73,
+ HEX_SREG_PCYCLE5T = 74,
+ HEX_SREG_PCYCLE6T = 75,
+ HEX_SREG_STFINST = 76,
+ HEX_SREG_ISDBCMD = 77,
+ HEX_SREG_ISDBVER = 78,
+ HEX_SREG_BRKPTINFO = 79,
+ HEX_SREG_S80 = 80,
+ HEX_SREG_COMMIT7T = 81,
+ HEX_SREG_COMMIT8T = 82,
+ HEX_SREG_PCYCLE7T = 83,
+ HEX_SREG_PCYCLE8T = 84,
+ HEX_SREG_COMMIT9T = 85,
+ HEX_SREG_COMMIT10T = 86,
+ HEX_SREG_COMMIT11T = 87,
+ HEX_SREG_COMMIT12T = 88,
+ HEX_SREG_COMMIT13T = 89,
+ HEX_SREG_COMMIT14T = 90,
+ HEX_SREG_COMMIT15T = 91,
+ HEX_SREG_COMMIT16T = 92,
+ HEX_SREG_PCYCLE9T = 93,
+ HEX_SREG_PCYCLE10T = 94,
+ HEX_SREG_PCYCLE11T = 95,
+ HEX_SREG_PCYCLE12T = 96,
+ HEX_SREG_PCYCLE13T = 97,
+ HEX_SREG_PCYCLE14T = 98,
+ HEX_SREG_PCYCLE15T = 99,
+ HEX_SREG_PCYCLE16T = 100,
+ HEX_SREG_IPEND = 101,
+ HEX_SREG_IAD = 102,
+ HEX_SREG_ISDBST1 = 103,
+ HEX_SREG_ISDBST2 = 104,
+ HEX_SREG_BRKPTINFO1 = 105,
};
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 7ad99ced7a..0d08ac7736 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -1600,38 +1600,53 @@ void HELPER(raise_stack_overflow)(CPUHexagonState *env, uint32_t slot,
void HELPER(ciad)(CPUHexagonState *env, uint32_t mask)
{
- uint32_t ipendad;
uint32_t iad;
HexagonCPU *cpu;
BQL_LOCK_GUARD();
cpu = env_archcpu(env);
- ipendad = hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
- env->threadId);
- iad = fGET_FIELD(ipendad, IPENDAD_IAD);
- fSET_FIELD(ipendad, IPENDAD_IAD, iad & ~(mask));
- hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD,
- ipendad, env->threadId);
+ if (cpu->cfg.hex_def->hex_version >= HEX_VER_V81) {
+ iad = hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IAD,
+ env->threadId) & ~mask;
+ hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IAD, iad,
+ env->threadId);
+ } else {
+ uint32_t ipendad =
+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
+ env->threadId);
+
+ fSET_FIELD(ipendad, IPENDAD_IAD,
+ fGET_FIELD(ipendad, IPENDAD_IAD) & ~mask);
+ hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD,
+ ipendad, env->threadId);
+ }
l2vic_clear_interrupt(cpu->l2vic);
hex_interrupt_update(env);
}
void HELPER(siad)(CPUHexagonState *env, uint32_t mask)
{
- uint32_t ipendad;
uint32_t iad;
HexagonCPU *cpu;
BQL_LOCK_GUARD();
cpu = env_archcpu(env);
- ipendad = cpu->globalregs ?
- hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
- env->threadId) : 0;
- iad = fGET_FIELD(ipendad, IPENDAD_IAD);
- fSET_FIELD(ipendad, IPENDAD_IAD, iad | mask);
if (cpu->globalregs) {
- hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD,
- ipendad, env->threadId);
+ if (cpu->cfg.hex_def->hex_version >= HEX_VER_V81) {
+ iad = hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IAD,
+ env->threadId) | mask;
+ hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IAD, iad,
+ env->threadId);
+ } else {
+ uint32_t ipendad =
+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,
+ env->threadId);
+
+ fSET_FIELD(ipendad, IPENDAD_IAD,
+ fGET_FIELD(ipendad, IPENDAD_IAD) | mask);
+ hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD,
+ ipendad, env->threadId);
+ }
}
hex_interrupt_update(env);
}
@@ -1657,7 +1672,7 @@ void HELPER(iassignw)(CPUHexagonState *env, uint32_t src)
CPU_FOREACH(cpu) {
CPUHexagonState *thread_env = &(HEXAGON_CPU(cpu)->env);
uint32_t imask = thread_env->t_sreg[HEX_SREG_IMASK];
- uint32_t intbitpos = (src >> 16) & 0xF;
+ uint32_t intbitpos = extract32(src, 16, 5);
uint32_t val = (src >> thread_env->threadId) & 0x1;
imask = deposit32(imask, intbitpos, 1, val);
thread_env->t_sreg[HEX_SREG_IMASK] = imask;
@@ -1677,7 +1692,7 @@ uint32_t HELPER(iassignr)(CPUHexagonState *env, uint32_t src)
BQL_LOCK_GUARD();
/* src fields are in same position as modectl, but mean different things */
- intbitpos = GET_FIELD(MODECTL_W, src);
+ intbitpos = extract32(src, 16, 5);
dest_reg = 0;
CPU_FOREACH(cpu) {
CPUHexagonState *thread_env = &(HEXAGON_CPU(cpu)->env);
@@ -1896,10 +1911,17 @@ static inline QEMU_ALWAYS_INLINE uint32_t sreg_read(CPUHexagonState *env,
}
return env->t_sreg[HEX_SREG_BADVA0];
}
+ cpu = env_archcpu(env);
+ if (reg == HEX_SREG_IPENDAD &&
+ cpu->cfg.hex_def->hex_version >= HEX_VER_V81) {
+ return (hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPEND,
+ env->threadId) & 0xffff) |
+ ((hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IAD,
+ env->threadId) & 0xffff) << 16);
+ }
if (reg < HEX_SREG_GLB_START) {
return env->t_sreg[reg];
}
- cpu = env_archcpu(env);
return cpu->globalregs ?
hexagon_globalreg_read(cpu->globalregs, reg, env->threadId) : 0;
}
diff --git a/target/hexagon/reg_fields_def.h.inc b/target/hexagon/reg_fields_def.h.inc
index a6b17011d8..c06e14fe24 100644
--- a/target/hexagon/reg_fields_def.h.inc
+++ b/target/hexagon/reg_fields_def.h.inc
@@ -152,3 +152,4 @@ DEF_REG_FIELD(ISDBST_PROCMODE, 3, 1)
DEF_REG_FIELD(ISDBST_MBXINSTATUS, 2, 1)
DEF_REG_FIELD(ISDBST_MBXOUTSTATUS, 1, 1)
DEF_REG_FIELD(ISDBST_READY, 0, 1)
+DEF_REG_FIELD(ISDBST2_DEBUGMODE, 16, 16)
diff --git a/target/hexagon/sys_macros.h b/target/hexagon/sys_macros.h
index 2e13ba00c8..a5b9b7f259 100644
--- a/target/hexagon/sys_macros.h
+++ b/target/hexagon/sys_macros.h
@@ -184,10 +184,14 @@
#define fIN_DEBUG_MODE(TNUM) ({ \
HexagonCPU *_cpu = env_archcpu(env); \
+ bool _is_v81 = _cpu->cfg.hex_def->hex_version >= HEX_VER_V81; \
uint32_t _isdbst = _cpu->globalregs ? \
hexagon_globalreg_read(_cpu->globalregs, \
- HEX_SREG_ISDBST, env->threadId) : 0; \
- (GET_FIELD(ISDBST_DEBUGMODE, _isdbst) \
+ _is_v81 ? HEX_SREG_ISDBST2 : HEX_SREG_ISDBST, \
+ env->threadId) : 0; \
+ ((_is_v81 ? \
+ GET_FIELD(ISDBST2_DEBUGMODE, _isdbst) : \
+ GET_FIELD(ISDBST_DEBUGMODE, _isdbst)) \
& (0x1 << (TNUM))) != 0; })
#define fIN_DEBUG_MODE_NO_ISDB(TNUM) false
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 5d3d67e5d3..fd1de87405 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -319,6 +319,8 @@ static bool sreg_write_ends_tb(int reg_num)
reg_num == HEX_SREG_STID ||
reg_num == HEX_SREG_IMASK ||
reg_num == HEX_SREG_IPENDAD ||
+ reg_num == HEX_SREG_IPEND ||
+ reg_num == HEX_SREG_IAD ||
reg_num == HEX_SREG_BESTWAIT ||
reg_num == HEX_SREG_SCHEDCFG;
}
@@ -830,8 +832,10 @@ static void gen_sreg_writes(DisasContext *ctx)
gen_helper_modify_ssr(tcg_env, ctx->t_sreg_new_value[reg_num],
old_reg);
} else if ((reg_num == HEX_SREG_STID) ||
- (reg_num == HEX_SREG_IMASK) ||
- (reg_num == HEX_SREG_IPENDAD)) {
+ (reg_num == HEX_SREG_IMASK) ||
+ (reg_num == HEX_SREG_IPENDAD) ||
+ (reg_num == HEX_SREG_IPEND) ||
+ (reg_num == HEX_SREG_IAD)) {
if (ctx->need_commit && reg_num < HEX_SREG_GLB_START) {
tcg_gen_mov_tl(hex_t_sreg[reg_num],
ctx->t_sreg_new_value[reg_num]);