Commit 533a789e13 for qemu.org
commit 533a789e13183161b47b42447c648b7811dfd7a8
Merge: 1743c1de16 18b664c900
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: Sat May 9 07:37:05 2026 -0400
Merge tag 'pull-target-arm-20260507' of https://gitlab.com/pm215/qemu into staging
target-arm queue:
* Initial experimental GICv5 interrupt controller emulation
* target/arm: Report IL=0 for Thumb 16-bit BKPT insn
* hw/misc/bcm2835_rng: Specify valid memory access sizes
# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmn8tN8ZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3kRED/43IeDEsDkxsikfrbZWqzQY
# Mpy3FDYeSa31XE0xcK97wbpEhwdzUdsyjR3lHIphHTOIit8XdrawySEtaA9k2pKc
# o1AmI8s2QReg0cM+Znwc9mSfDi52ExxrVEObGUBa27RVtX06jY9nwrUfegAaMMW5
# bIljGTc6b9U5XEbxe2qF53BeQouYtgsSLInA5ID6TtZwocw/sSYyIwEmJ7AVGvX/
# 6BepwjYg6jWTqZ884YNuUK4PAFMxgsxtowEI3D7Frxc0sPOxzZYitp5hrnQwZJdo
# 7omXk3VVEjOsJRztdy6Ulxw4+atb4zLcZRHIi96w719/Q7dUmLggK2ZG1FmMHNat
# TevJFEmg5eYjdXWEodIRCHCpGXBxzUFzfh8lEGW5afsjxQMRABgKHv9e5bcpmyT+
# +YpgWgscC2FJTv6/E6Qjy4VYLjyUHbqsUWtr+5OZFb8pHd9DWO5gGwZE2RhDwKUI
# RaCrMneVhPWDHfyauIgAQ1K2DdDRr8a75mDVbH620ldxyoetKnork7huE1qwKC32
# be46fk9u6/KcyafbQQCiZe3KzqoKxpvJPsu5tlsvLtuzEgz6pQdI5j0NsS0k3Ow8
# VSfynqAFaCUNZaJNqLj6Inj9YOqYzxu+6RmB3s+L1+Aj2QxHiPQJjbggCHJOPTo0
# 2uyaQodquIbdfBabUpgtlg==
# =B0BC
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 07 May 2026 11:50:55 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20260507' of https://gitlab.com/pm215/qemu: (67 commits)
hw/misc/bcm2835_rng: Specify valid memory access sizes
target/arm: Report IL=0 for Thumb 16-bit BKPT insn
hw/arm/virt: Allow user to select GICv5
hw/arm/virt: Enable GICv5 CPU interface when using GICv5
hw/arm/virt: Use correct interrupt type for GICv5 SPIs in the DTB
hw/arm/virt: Handle GICv5 in interrupt bindings for PPIs
hw/arm/virt: Advertise GICv5 in the DTB
hw/arm/virt: Create and connect GICv5
hw/arm/virt: Split GICv2 and GICv3/4 creation
hw/arm/virt: Pull "wire CPU interrupts" out of create_gic()
hw/arm/virt: Move MSI controller creation out of create_gic()
hw/arm/virt: Remember CPU phandles rather than looking them up by name
hw/intc/arm_gicv3_cpuif: Don't allow GICv3 if CPU has GICv5 cpuif
target/arm: Add has_gcie property to enable FEAT_GCIE
target/arm: Connect internal interrupt sources up as GICv5 PPIs
target/arm: GICv5 cpuif: Signal IRQ or FIQ
target/arm: GICv5 cpuif: Implement GIC CDDI
hw/intc/arm_gicv5: Implement Deactivate command
target/arm: GICv5 cpuif: Implement GIC CDEOI
target/arm: GICv5 cpuif: Implement GICR CDIA command
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>