Commit 56c0c25d5a for qemu.org

commit 56c0c25d5aab2e14de406f1e65ab25158f7507d9
Merge: ab2056a0b7 ec7d324287
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date:   Fri Jul 10 07:11:03 2026 +0200

    Merge tag 'pull-riscv-to-apply-20260710' of https://github.com/alistair23/qemu into staging

    RISC-V PR for 11.1

    * Fix IOMMU fault type for spa_fetch() faults
    * Check IOMMU for reserved PTE bits
    * Fault when IOMMU !PTE_U and no priv access
    * Fault IOMMU for non-user PTE in G_STAGE
    * Check IOMMU reserved MSI PTE basic bits
    * Record fault on IOMMU-generated MSI write
    * Move RISC-V TCG files and fix --disable-tcg
    * Check for misaligned IOMMU IOHGATP_PPN
    * Update IOMMU ioval2 when faulting in spa_fetch()
    * Forbid IOMMU GATE/SADE if caps.AMO_HWADD is zero
    * Set IOMMU ftype and iova in riscv_iommu_ctx()
    * Check PCIe DOE mailbox length for overflows
    * Add extensions after v7.1-rc4 update
    * Remove job building OpenSBI firmware binaries
    * Correct ACPI field sequence in SPCR table

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    * tag 'pull-riscv-to-apply-20260710' of https://github.com/alistair23/qemu: (40 commits)
      tests: update SPCR loongarch64 and riscv64 test data
      hw/acpi: correct field sequence in SPCR table
      tests: allow differences in SPCR
      gitlab-ci: Remove job building OpenSBI firmware binaries
      target/riscv/kvm: add extensions after v7.1-rc4 update
      hw/pci/pcie_doe: Check mailbox length for overflows
      hw/riscv/riscv-iommu.c: set ftype and iova in riscv_iommu_ctx()
      hw/riscv/riscv-iommu: forbid GATE/SADE if caps.AMO_HWADD is zero
      hw/riscv/riscv-iommu.c: update ioval2 when faulting in spa_fetch()
      hw/riscv/riscv-iommu.c: check for misaligned IOHGATP_PPN
      gitlab-ci.d/crossbuilds: add riscv64 KVM-only build job
      target/riscv: move riscv_cpu_set_aia_ireg_rmw_cb() to riscv_imsic
      target/riscv: move riscv_cpu_set_geilen() to riscv-imsic
      target/riscv/tcg: remove unused riscv_cpu_get_geilen()
      target/riscv: move riscv_cpu_set_rdtime_fn to riscv_aclint
      target/riscv/gdbstub.c: isolate TCG only checks
      hw/riscv/riscv_hart.c isolate tcg only bits
      target/riscv/cpu.c: filter TCG only bits in riscv_cpu_reset_hold()
      target/riscv: gate riscv_cpu_update_mip with tcg_enabled()
      target/riscv/cpu.c: handle TCG bits of riscv_cpu_dump_state
      ...

    Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>