Commit 5a2efa3cfe for qemu.org

commit 5a2efa3cfebfc73f88f94b287aefa4801828b5a5
Author: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Date:   Tue Sep 1 20:20:40 2026 +0000

    hw/riscv: remove TYPE_TARGET_{RISCV32,RISCV64}_MACHINE

    Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
    Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
    Message-ID: <20260901202043.26532-12-pierrick.bouvier@oss.qualcomm.com>
    Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>

diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c
index 2aa748233b..2f008c4a70 100644
--- a/hw/core/null-machine.c
+++ b/hw/core/null-machine.c
@@ -56,7 +56,4 @@ static void machine_none_machine_init(MachineClass *mc)
     mc->no_cdrom = 1;
 }

-DEFINE_MACHINE_WITH_INTERFACES("none", machine_none_machine_init,
-                               { TYPE_TARGET_RISCV32_MACHINE },
-                               { TYPE_TARGET_RISCV64_MACHINE },
-                               { })
+DEFINE_MACHINE("none", machine_none_machine_init)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index d58656f70d..d2ae321a37 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1811,8 +1811,6 @@ static const TypeInfo virt_machine_typeinfo = {
     .instance_size = sizeof(RISCVVirtState),
     .interfaces = (const InterfaceInfo[]) {
          { TYPE_HOTPLUG_HANDLER },
-         { TYPE_TARGET_RISCV32_MACHINE },
-         { TYPE_TARGET_RISCV64_MACHINE },
          { }
     },
 };
diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qom.h
index ee346227bb..6c0bbdfc15 100644
--- a/include/hw/riscv/machines-qom.h
+++ b/include/hw/riscv/machines-qom.h
@@ -11,12 +11,6 @@

 #include "hw/core/boards.h"

-#define TYPE_TARGET_RISCV32_MACHINE \
-        "target-info-riscv32-machine"
-
-#define TYPE_TARGET_RISCV64_MACHINE \
-        "target-info-riscv64-machine"
-
 /*
  * Interfaces specifying whether a given QOM object is available in
  * qemu-system-riscv32, qemu-system-riscv64, or both.
diff --git a/target-info-qom.c b/target-info-qom.c
index 7959853e0d..f98d3d7698 100644
--- a/target-info-qom.c
+++ b/target-info-qom.c
@@ -14,19 +14,6 @@
 #include "qemu/target-info-qom.h"
 #include "hw/riscv/machines-qom.h"

-static const TypeInfo target_info_types[] = {
-    {
-        .name           = TYPE_TARGET_RISCV32_MACHINE,
-        .parent         = TYPE_INTERFACE,
-    },
-    {
-        .name           = TYPE_TARGET_RISCV64_MACHINE,
-        .parent         = TYPE_INTERFACE,
-    },
-};
-
-DEFINE_TYPES(target_info_types)
-
 static void target_info_qom_class_init(ObjectClass *oc, const void * data)
 {
     TargetInfoQomClass *klass = TARGET_INFO_CLASS(oc);
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 31c49ca3e6..59676c9447 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -582,17 +582,13 @@ const VMStateDescription vmstate_riscv_cpu = {
 };

 const InterfaceInfo riscv32_machine_interfaces[] = {
-    { TYPE_TARGET_RISCV32_MACHINE },
     { }
 };

 const InterfaceInfo riscv64_machine_interfaces[] = {
-    { TYPE_TARGET_RISCV64_MACHINE },
     { }
 };

 const InterfaceInfo riscv32_64_machine_interfaces[] = {
-    { TYPE_TARGET_RISCV32_MACHINE },
-    { TYPE_TARGET_RISCV64_MACHINE },
     { }
 };