Commit 5f5875b0b5 for qemu.org

commit 5f5875b0b57efca88cf658eb281903ed75ca8c7d
Merge: 3e8d341ef1 38937473da
Author: Peter Maydell <peter.maydell@linaro.org>
Date:   Fri Mar 20 10:04:40 2026 +0000

    Merge tag 'pull-riscv-to-apply-20260320' of https://github.com/alistair23/qemu into staging

    RISC-V PR for 11.

    * Fix integer overflow in cm_base calculation
    * Fix null pointer dereference in cpu_set_exception_base
    * Update Daniel Henrique Barboza's email
    * Add Chao Liu as reviewer
    * Set SiFive PDMA done bit upon completion
    * Remove deprecated 'riscv, delegate' device-tree property
    * Fix OCP FP8 E4M3 conversion issues
    * Fix IOMMU instance_init allocations in instance_finalize
    * Support Smpmpmt extension
    * Fix SiFive UART spurious IRQ issue and misc updates
    * Fix missing flags merge in probe_pages for cross-page accesses
    * Fix page probe issues in vext_ldff
    * Fix scountovf CSR behavior in VS-mode and M-mode

    # -----BEGIN PGP SIGNATURE-----
    #
    # iQIzBAABCgAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmm8ha4ACgkQr3yVEwxT
    # gBMKOBAAsB6CwDSsi+DmuCD5r25kaLtvFg7hqc6iYpzjuwUE+uHu3LWMky19Div1
    # mpMLZi1an/NbIKX8N9KS1G87hzteqvxY4wKVoMn1mF/3yQ5r6OJ2SfZoDiiJyAva
    # UIhaiRUbmg78OX0YCBYCWaRbqN7rbV6XJnB8oGUyhVNwtfJ/pZppfCflsd5+E3KD
    # U7sKMVaytfeQCQGXeNYgZBvYvDQ7/t21eLytLYGhUNy89N8mo7V5egFJEN45BE8O
    # Zh+Oa7bN+lUOg0eUTj98zwXXXeOZMEKbn5I01XuUH1gn5aO+CeEvFEqDssF1fKle
    # mq00WkK1Tk9kZOTLhMR4pdW2kXkom/mEmXI9jU0CInmF63+r8/SugimPS8LyLE3N
    # qZodmmEeckOPsE+RnmBOHww2Y+g668+C/sTcSAuHsWUXJLDty+DyO0RU4d0ioRHa
    # zyOf2cNoSVV8EWJ5uHk9Et2eimq0Q83n/tVpkKyq877rOGLQzoDIKJEwIO7nI59x
    # NF437R7hWKOZ0JLE22wuLWNW8LohxaFkzYRGFDH2/qKlsEv7mSkutTU4y6g0XKok
    # iTjBaibmwsaDeMrf5JYHTGMSvF/3lIXyeJiBCq6uQac3fFXKKeehttaU4F+KW0KE
    # gO6oUdJWExp7Tt+9nx5KqFxlJPNd/JV3gDCKRjQskW3bT4H1cco=
    # =chEj
    # -----END PGP SIGNATURE-----
    # gpg: Signature made Thu Mar 19 23:24:30 2026 GMT
    # gpg:                using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
    # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
    # gpg: WARNING: This key is not certified with a trusted signature!
    # gpg:          There is no indication that the signature belongs to the owner.
    # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65  9296 AF7C 9513 0C53 8013

    * tag 'pull-riscv-to-apply-20260320' of https://github.com/alistair23/qemu:
      target/riscv: Fix scountovf CSR behavior in VS-mode and M-mode
      target/riscv: rvv: Fix page probe issues in vext_ldff
      target/riscv: rvv: Fix missing flags merge in probe_pages for cross-page accesses
      hw/char: sifive_uart: Remove ip variable
      hw/char: sifive_uart: Update IRQ when rxctrl is written
      hw/char: sifive_uart: Sync txwm interrupt pending status after TX FIFO enqueue
      hw/char: sifive_uart: Implement txctrl.txen and rxctrl.rxen
      target/riscv: Support Smpmpmt extension
      hw/riscv/riscv-iommu: Free instance_init allocations in instance_finalize
      fpu: Fix unexpected exception flags when converting infinity to OCP E4M3
      fpu: Fix repacking issues in the uncanonical step for E4M3 overflow
      hw/riscv: Remove deprecated 'riscv, delegate' device-tree property
      hw/dma: sifive_pdma: Set done bit upon completion
      MAINTAINERS: Add myself as a reviewer for RISC-V TCG CPUs
      MAINTAINERS: update my email
      target/riscv: Fix null pointer dereference in cpu_set_exception_base
      hw/riscv: Fix integer overflow in cm_base calculation

    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>