Commit 628d071bc5 for qemu.org

commit 628d071bc5794211ae99e4f6edddebfac4902c80
Author: Brian Cain <brian.cain@oss.qualcomm.com>
Date:   Tue Sep 8 21:01:32 2026 -0700

    target/hexagon: add Y2_tlbpp as unimplemented

    Y2_tlbpp is mostly associated with the not-yet-implemented DMA
    engine.  Let's decode it as unimpl for now.

    Reviewed-by: Marco Liebel <marco.liebel@oss.qualcomm.com>
    Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc
index 8b4eb27d68..5a98ea3313 100644
--- a/target/hexagon/attribs_def.h.inc
+++ b/target/hexagon/attribs_def.h.inc
@@ -25,6 +25,7 @@ DEF_ATTRIB(NA_NT, "Non-Allocating Non-Temporal instruction", "", "")

 DEF_ATTRIB(PRIV, "Not available in user or guest mode", "", "")
 DEF_ATTRIB(GUEST, "Not available in user mode", "", "")
+DEF_ATTRIB(TLBPP_INSN, "Extended (64-bit VA) TLB probe instruction", "", "")

 DEF_ATTRIB(FPOP, "Floating Point Operation", "", "")

diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/imported/encode_pp.def
index fca8f8aeb1..4b307b97b3 100644
--- a/target/hexagon/imported/encode_pp.def
+++ b/target/hexagon/imported/encode_pp.def
@@ -890,6 +890,7 @@ DEF_ENC32(Y2_tlbunlock,ICLASS_CR" 1100 001----- PP------ 010-----")
 DEF_ENC32(Y2_k0lock,   ICLASS_CR" 1100 001----- PP------ 011-----")
 DEF_ENC32(Y2_k0unlock, ICLASS_CR" 1100 001----- PP------ 100-----")
 DEF_ENC32(Y2_tlbp,     ICLASS_CR" 1100 100sssss PP------ ---ddddd")
+DEF_ENC32(Y2_tlbpp,"01101100011sssssPP---------ddddd")
 DEF_ENC32(Y5_tlboc,    ICLASS_CR" 1100 111sssss PP------ ---ddddd")
 DEF_ENC32(Y5_tlbasidi, ICLASS_CR" 1100 101sssss PP------ --------")
 DEF_ENC32(Y2_tlbr,     ICLASS_CR" 1100 010sssss PP------ ---ddddd")
diff --git a/target/hexagon/imported/system.idef b/target/hexagon/imported/system.idef
index 6187ada5ab..a58da8f826 100644
--- a/target/hexagon/imported/system.idef
+++ b/target/hexagon/imported/system.idef
@@ -118,6 +118,8 @@ Q6INSN(Y2_tlbr,"Rdd32=tlbr(Rs32)", ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_

 Q6INSN(Y2_tlbp,"Rd32=tlbp(Rs32)", ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET), "Probe TLB", {RdV=fTLBP(RsV);})

+Q6INSN(Y2_tlbpp,"Rd32=tlbp(Rss32)", ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_TLBPP_INSN), "Probe TLB64", {RdV=fTLBPP(RssV);})
+
 Q6INSN(Y5_tlbasidi,"tlbinvasid(Rs32)",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET), "Invalidate ASID",
 {
 	fHIDE(int i;)
diff --git a/target/hexagon/sys_macros.h b/target/hexagon/sys_macros.h
index a49c72715d..2e13ba00c8 100644
--- a/target/hexagon/sys_macros.h
+++ b/target/hexagon/sys_macros.h
@@ -177,6 +177,9 @@
                      fTLB_NONPOW2WRAP(fTLB_IDXMASK(INDEX)))
 #define fTLBP(TLBHI) \
     hex_tlb_lookup(env, ((TLBHI) >> 12), ((TLBHI) << 12))
+#define fTLBPP(TLBHI) ({ \
+    qemu_log_mask(LOG_UNIMP, "tlbpp is not implemented\n"); \
+    0; })
 #define iic_flush_cache(p)

 #define fIN_DEBUG_MODE(TNUM) ({ \
diff --git a/target/hexagon/tag_rev_info.c.inc b/target/hexagon/tag_rev_info.c.inc
index 48bdc52bfd..68be8cbafb 100644
--- a/target/hexagon/tag_rev_info.c.inc
+++ b/target/hexagon/tag_rev_info.c.inc
@@ -642,6 +642,8 @@ static const struct tag_rev_info tag_rev_info[XX_LAST_OPCODE] = {
     [S2_storeri_pi_nt] = { .introduced = HEX_VER_V79, .removed = HEX_VER_NONE },
     [Y2_dcfetchbo_nt] = { .introduced = HEX_VER_V79, .removed = HEX_VER_NONE },
     [Y2_dczeroa_nt] = { .introduced = HEX_VER_V79, .removed = HEX_VER_NONE },
+
+    [Y2_tlbpp] = { .introduced = HEX_VER_V81, .removed = HEX_VER_NONE },
 };

 #endif /* HEXAGON_TAG_ARCH_TABLE_H */