Commit 65152c2942 for qemu.org

commit 65152c2942c388c0ea0ae9e13aaa91a35710855f
Author: Tao Tang <tangtao1634@phytium.com.cn>
Date:   Wed Mar 4 22:23:42 2026 +0800

    hw/arm/smmuv3-common: Fix incorrect reserved mask for SMMU CR0 register

    The current definition of the SMMU_CR0_RESERVED mask is incorrect.
    It mistakenly treats bit 10 (DPT_WALK_EN) as a reserved bit while
    treating bit 9 (RES0) as an implemented bit.

    According to the SMMU architecture specification, the layout for CR0 is:
    | 31:11| RES0           |
    | 10   | DPT_WALK_EN    |
    | 9    | RES0           |
    | 8:6  | VMW            |
    | 5    | RES0           |
    | 4    | ATSCHK         |
    | 3    | CMDQEN         |
    | 2    | EVENTQEN       |
    | 1    | PRIQEN         |
    | 0    | SMMUEN         |

    Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn>
    Reviewed-by: Eric Auger <eric.auger@redhat.com>
    Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
    Reviewed-by: Mostafa Saleh <smostafa@google.com>
    Message-id: 20260304142344.3341444-2-tangtao1634@phytium.com.cn
    Fixes: fae4be38b35 ("hw/arm/smmuv3: Implement MMIO write operations")
    Link: https://lists.gnu.org/archive/html/qemu-arm/2025-06/msg00088.html
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h
index 67a23fbeaa..2df54ba60f 100644
--- a/include/hw/arm/smmuv3-common.h
+++ b/include/hw/arm/smmuv3-common.h
@@ -355,7 +355,7 @@ REG32(CR0,                 0x20)
     FIELD(CR0, EVENTQEN,      2, 1)
     FIELD(CR0, CMDQEN,        3, 1)

-#define SMMU_CR0_RESERVED 0xFFFFFC20
+#define SMMU_CR0_RESERVED 0xFFFFFA20

 REG32(CR0ACK,              0x24)
 REG32(CR1,                 0x28)