Commit 6802b477e1 for qemu.org

commit 6802b477e14c34d09fbf095d1d20343b83bc5636
Author: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>
Date:   Thu Jan 15 13:01:16 2026 +0000

    hw/riscv: Fix integer overflow in cm_base calculation

    Ensure 64-bit arithmetic is used when computing cm_base,
    avoiding potential integer overflow.

    Resolves: Coverity CID 1644076

    Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
    Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
    Message-ID: <20260115130110.2825796-2-djordje.todorovic@htecgroup.com>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/include/hw/riscv/cps.h b/include/hw/riscv/cps.h
index f33fd7ac86..39029bca8f 100644
--- a/include/hw/riscv/cps.h
+++ b/include/hw/riscv/cps.h
@@ -27,7 +27,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(RISCVCPSState, RISCV_CPS)
 /* The global CM base for the boston-aia model. */
 #define GLOBAL_CM_BASE 0x16100000
 /* The CM block is 512 KiB. */
-#define CM_SIZE (1 << 19)
+#define CM_SIZE (1ULL << 19)

 /*
  * The mhartid bits has cluster at bit 16, core at bit 4, and hart at