Commit 6d8675548e for qemu.org
commit 6d8675548ecd877a2553ba3f962406f9938d372b
Author: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Date: Tue Sep 1 20:20:41 2026 +0000
hw/riscv: remove {riscv32, riscv32_64, riscv64}_machine_interfaces
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260901202043.26532-13-pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c
index 558f30b97e..72d50d369a 100644
--- a/hw/riscv/k230.c
+++ b/hw/riscv/k230.c
@@ -556,7 +556,6 @@ static const TypeInfo k230_machine_typeinfo = {
.class_init = k230_machine_class_init,
.instance_init = k230_machine_instance_init,
.instance_size = sizeof(K230MachineState),
- .interfaces = riscv64_machine_interfaces,
};
static void k230_machine_init_register_types(void)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 4017129c83..42d4fc3973 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -756,7 +756,6 @@ static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
.class_init = microchip_icicle_kit_machine_class_init,
.instance_init = microchip_icicle_kit_machine_instance_init,
.instance_size = sizeof(MicrochipIcicleKitState),
- .interfaces = riscv64_machine_interfaces,
};
static void microchip_icicle_kit_machine_init_register_types(void)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 5b2f33d5ac..c58d899330 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -338,7 +338,6 @@ static const TypeInfo open_titan_types[] = {
.parent = TYPE_MACHINE,
.instance_size = sizeof(OpenTitanState),
.class_init = opentitan_machine_class_init,
- .interfaces = riscv32_machine_interfaces,
}
};
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index 835b1f879b..9fd7856dc2 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -98,7 +98,6 @@ static const TypeInfo shakti_c_machine_type_info = {
.class_init = shakti_c_machine_class_init,
.instance_init = shakti_c_machine_instance_init,
.instance_size = sizeof(ShaktiCMachineState),
- .interfaces = riscv64_machine_interfaces,
};
static void shakti_c_machine_type_info_register(void)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 71925583bd..ede7cb52f0 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -168,7 +168,6 @@ static const TypeInfo sifive_e_machine_typeinfo = {
.class_init = sifive_e_machine_class_init,
.instance_init = sifive_e_machine_instance_init,
.instance_size = sizeof(SiFiveEState),
- .interfaces = riscv32_64_machine_interfaces,
};
static void sifive_e_machine_init_register_types(void)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 57a57c96e1..08687cfc36 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -680,7 +680,6 @@ static const TypeInfo sifive_u_machine_typeinfo = {
.class_init = sifive_u_machine_class_init,
.instance_init = sifive_u_machine_instance_init,
.instance_size = sizeof(SiFiveUState),
- .interfaces = riscv32_64_machine_interfaces,
};
static void sifive_u_machine_init_register_types(void)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 630b65f569..3786de4b0b 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -292,7 +292,6 @@ static const TypeInfo spike_machine_typeinfo = {
.class_init = spike_machine_class_init,
.instance_init = spike_machine_instance_init,
.instance_size = sizeof(SpikeState),
- .interfaces = riscv32_64_machine_interfaces,
};
static void spike_machine_init_register_types(void)
diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c
index d808bcc11c..5e155726ab 100644
--- a/hw/riscv/tt_atlantis.c
+++ b/hw/riscv/tt_atlantis.c
@@ -609,7 +609,6 @@ static const TypeInfo tt_atlantis_types[] = {
.parent = TYPE_MACHINE,
.class_init = tt_atlantis_machine_class_init,
.instance_size = sizeof(TTAtlantisState),
- .interfaces = riscv64_machine_interfaces,
},
};
diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c
index 384624d69a..e02624b62b 100644
--- a/hw/riscv/xiangshan_kmh.c
+++ b/hw/riscv/xiangshan_kmh.c
@@ -216,7 +216,6 @@ static const TypeInfo xiangshan_kmh_machine_info = {
.parent = TYPE_MACHINE,
.instance_size = sizeof(XiangshanKmhState),
.class_init = xiangshan_kmh_machine_class_init,
- .interfaces = riscv64_machine_interfaces,
};
static void xiangshan_kmh_machine_register_types(void)
diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qom.h
index 6c0bbdfc15..e5f45b32e6 100644
--- a/include/hw/riscv/machines-qom.h
+++ b/include/hw/riscv/machines-qom.h
@@ -11,15 +11,6 @@
#include "hw/core/boards.h"
-/*
- * Interfaces specifying whether a given QOM object is available in
- * qemu-system-riscv32, qemu-system-riscv64, or both.
- */
-
-extern const InterfaceInfo riscv32_machine_interfaces[];
-extern const InterfaceInfo riscv64_machine_interfaces[];
-extern const InterfaceInfo riscv32_64_machine_interfaces[];
-
/*
* Helper macros for defining machines available in qemu-system-riscv32,
* qemu-system-riscv64, or both.
@@ -27,14 +18,14 @@ extern const InterfaceInfo riscv32_64_machine_interfaces[];
#define DEFINE_MACHINE_RISCV32(namestr, machine_initfn) \
DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- riscv32_machine_interfaces)
+ NULL)
#define DEFINE_MACHINE_RISCV64(namestr, machine_initfn) \
DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- riscv64_machine_interfaces)
+ NULL)
#define DEFINE_MACHINE_RISCV32_64(namestr, machine_initfn) \
DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- riscv32_64_machine_interfaces)
+ NULL)
#endif
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 59676c9447..22a918cec9 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -580,15 +580,3 @@ const VMStateDescription vmstate_riscv_cpu = {
NULL
}
};
-
-const InterfaceInfo riscv32_machine_interfaces[] = {
- { }
-};
-
-const InterfaceInfo riscv64_machine_interfaces[] = {
- { }
-};
-
-const InterfaceInfo riscv32_64_machine_interfaces[] = {
- { }
-};