Commit 74bbc9ec77 for qemu.org
commit 74bbc9ec77a72b7d54442c583613839d686aa54b
Author: Brian Cain <brian.cain@oss.qualcomm.com>
Date: Tue Sep 8 21:01:33 2026 -0700
hw/hexagon: add the V81DGB_1 and V81QA_1 machines
Add these new machines that correspond to the hexagon-sim machine types.
Reviewed-by: Marco Liebel <marco.liebel@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
diff --git a/hw/hexagon/hexagon_dsp.c b/hw/hexagon/hexagon_dsp.c
index ff110234b0..be17a32ee1 100644
--- a/hw/hexagon/hexagon_dsp.c
+++ b/hw/hexagon/hexagon_dsp.c
@@ -30,6 +30,8 @@
#include "machine_cfg_v66g_1024.h.inc"
#include "machine_cfg_v68n_1024.h.inc"
+#include "machine_cfg_v81dgb_1.h.inc"
+#include "machine_cfg_v81qa_1.h.inc"
#define TYPE_HEXAGON_DSP_MACHINE "hexagon-dsp-machine"
OBJECT_DECLARE_SIMPLE_TYPE(HexagonDspMachineState, HEXAGON_DSP_MACHINE)
@@ -199,6 +201,40 @@ static void v68n_1024_init(ObjectClass *oc, const void *data)
mc->default_cpus = 6;
}
+static void v81dgb_1_config_init(MachineState *machine)
+{
+ hexagon_common_init(machine, v81dgb_1_rev, &v81dgb_1);
+}
+
+static void v81dgb_1_init(ObjectClass *oc, const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "Hexagon V81DGB_1";
+ mc->init = v81dgb_1_config_init;
+ init_mc(mc);
+ mc->default_cpu_type = TYPE_HEXAGON_CPU_V81;
+ mc->max_cpus = 12;
+ mc->default_cpus = 12;
+}
+
+static void v81qa_1_config_init(MachineState *machine)
+{
+ hexagon_common_init(machine, v81_rev, &v81qa_1);
+}
+
+static void v81qa_1_init(ObjectClass *oc, const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "Hexagon V81QA_1";
+ mc->init = v81qa_1_config_init;
+ init_mc(mc);
+ mc->default_cpu_type = TYPE_HEXAGON_CPU_V81;
+ mc->max_cpus = 12;
+ mc->default_cpus = 12;
+}
+
static const TypeInfo hexagon_machine_types[] = {
{
.name = TYPE_HEXAGON_COMMON_MACHINE,
@@ -222,6 +258,16 @@ static const TypeInfo hexagon_machine_types[] = {
.parent = TYPE_HEXAGON_DSP_MACHINE,
.class_init = v68n_1024_init,
},
+ {
+ .name = MACHINE_TYPE_NAME("V81DGB_1"),
+ .parent = TYPE_HEXAGON_DSP_MACHINE,
+ .class_init = v81dgb_1_init,
+ },
+ {
+ .name = MACHINE_TYPE_NAME("V81QA_1"),
+ .parent = TYPE_HEXAGON_DSP_MACHINE,
+ .class_init = v81qa_1_init,
+ },
};
DEFINE_TYPES(hexagon_machine_types)
diff --git a/hw/hexagon/machine_cfg_v81dgb_1.h.inc b/hw/hexagon/machine_cfg_v81dgb_1.h.inc
new file mode 100644
index 0000000000..c7d9e7e192
--- /dev/null
+++ b/hw/hexagon/machine_cfg_v81dgb_1.h.inc
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+static const struct hexagon_machine_config v81dgb_1 = {
+ .cfgbase = 0xd8380000,
+ .l2tcm_size = 0x00000000,
+ .l2vic_base = 0xfc910000,
+ .l2vic_size = 0x00001000,
+ .csr_base = 0xfc900000,
+ .qtmr_region = 0xfc921000,
+ .cfgtable = {
+ .l2tcm_base = 0x0000d800,
+ .reserved0 = 0x00000000,
+ .subsystem_base = 0x0000fc90,
+ .etm_base = 0x0000d839,
+ .l2cfg_base = 0x0000d83a,
+ .reserved1 = 0x0000d83b,
+ .l1s0_base = 0x0000d840,
+ .axi2_lowaddr = 0x00000000,
+ .streamer_base = 0x00000000,
+ .reserved2 = 0x00000000,
+ .fastl2vic_base = 0x0000d83e,
+ .jtlb_size_entries = 0x000000c0,
+ .coproc_present = 0x00000005,
+ .ext_contexts = 0x00000004,
+ .vtcm_base = 0x0000d840,
+ .vtcm_size_kb = 0x00000800,
+ .l2tag_size = 0x00000800,
+ .l2ecomem_size = 0x00000800,
+ .thread_enable_mask = 0x00000fff,
+ .eccreg_base = 0x00000000,
+ .l2line_size = 0x00000080,
+ .tiny_core = 0x00000000,
+ .l2itcm_size = 0x00000000,
+ .l2itcm_base = 0x0000d800,
+ .reserved3 = 0x00000000,
+ .dtm_present = 0x00000000,
+ .dma_version = 0x00000000,
+ .hvx_vec_log_length = 0x00000007,
+ .core_id = 0x00000000,
+ .core_count = 0x00000000,
+ .coproc2_reg0 = 0x00000001,
+ .coproc2_reg1 = 0x00000000,
+ .v2x_mode = 0x00000000,
+ .coproc2_reg2 = 0x00000000,
+ .coproc2_reg3 = 0x00000000,
+ .coproc2_reg4 = 0x00000000,
+ .coproc2_reg5 = 0x00000000,
+ .coproc2_reg6 = 0x00000000,
+ .coproc2_reg7 = 0x00000000,
+ .acd_preset = 0x00000000,
+ .mnd_preset = 0x00000000,
+ .l1d_size_kb = 0x00000040,
+ .l1i_size_kb = 0x00000040,
+ .l1d_write_policy = 0x00000002,
+ .vtcm_bank_width = 0x00000080,
+ .reserved4 = 0x00000000,
+ .reserved5 = 0x00000000,
+ .reserved6 = 0x00000000,
+ .coproc2_cvt_mpy_size = 0x00000000,
+ .consistency_domain = 0x000000e0,
+ .capacity_domain = 0x00000080,
+ .axi3_lowaddr = 0x00004000,
+ .coproc2_int8_subcolumns = 0x00000000,
+ .corecfg_present = 0x0000000d,
+ .coproc2_fp16_acc_exp = 0x00000000,
+ .AXIM2_secondary_base = 0x00000000,
+ .AXIM_data_width = 0x00000000,
+ .l1d_ways = 0x00000008,
+ .l1i_ways = 0x00000004,
+ .l2way_num = 0x00000008,
+ .dma_jtlb_entries = 0x00000040,
+ },
+};
diff --git a/hw/hexagon/machine_cfg_v81qa_1.h.inc b/hw/hexagon/machine_cfg_v81qa_1.h.inc
new file mode 100644
index 0000000000..8fb9bcb174
--- /dev/null
+++ b/hw/hexagon/machine_cfg_v81qa_1.h.inc
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+static const struct hexagon_machine_config v81qa_1 = {
+ .cfgbase = 0xd8380000,
+ .l2tcm_size = 0x00000000,
+ .l2vic_base = 0xfc910000,
+ .l2vic_size = 0x00001000,
+ .csr_base = 0xfc900000,
+ .qtmr_region = 0xfc921000,
+ .cfgtable = {
+ .l2tcm_base = 0x0000d800,
+ .reserved0 = 0x00000000,
+ .subsystem_base = 0x00002000,
+ .etm_base = 0x0000d819,
+ .l2cfg_base = 0x0000d81a,
+ .reserved1 = 0x0000d81b,
+ .l1s0_base = 0x0000d900,
+ .axi2_lowaddr = 0x00000000,
+ .streamer_base = 0x00000000,
+ .reserved2 = 0x00000000,
+ .fastl2vic_base = 0x0000d81e,
+ .jtlb_size_entries = 0x00000080,
+ .coproc_present = 0x0000000d,
+ .ext_contexts = 0x00000008,
+ .vtcm_base = 0x0000d900,
+ .vtcm_size_kb = 0x00004000,
+ .l2tag_size = 0x00000400,
+ .l2ecomem_size = 0x00000400,
+ .thread_enable_mask = 0x00000fff,
+ .eccreg_base = 0x0000d81f,
+ .l2line_size = 0x00000080,
+ .tiny_core = 0x00000000,
+ .l2itcm_size = 0x00000000,
+ .l2itcm_base = 0x0000d800,
+ .reserved3 = 0x00000000,
+ .dtm_present = 0x00000000,
+ .dma_version = 0x00000008,
+ .hvx_vec_log_length = 0x00000007,
+ .core_id = 0x00000000,
+ .core_count = 0x00000000,
+ .coproc2_reg0 = 0x00000010,
+ .coproc2_reg1 = 0x00000008,
+ .v2x_mode = 0x00000001,
+ .coproc2_reg2 = 0x00000000,
+ .coproc2_reg3 = 0x00000000,
+ .coproc2_reg4 = 0x00000000,
+ .coproc2_reg5 = 0x00000000,
+ .coproc2_reg6 = 0x00000000,
+ .coproc2_reg7 = 0x00000000,
+ .acd_preset = 0x00000001,
+ .mnd_preset = 0x00000001,
+ .l1d_size_kb = 0x00000040,
+ .l1i_size_kb = 0x00000040,
+ .l1d_write_policy = 0x00000002,
+ .vtcm_bank_width = 0x00000080,
+ .reserved4 = 0x00000001,
+ .reserved5 = 0x00000000,
+ .reserved6 = 0x00000000,
+ .coproc2_cvt_mpy_size = 0x00000000,
+ .consistency_domain = 0x000000e0,
+ .capacity_domain = 0x00000080,
+ .axi3_lowaddr = 0x00004000,
+ .coproc2_int8_subcolumns = 0x00000000,
+ .corecfg_present = 0x0000000d,
+ .coproc2_fp16_acc_exp = 0x00000001,
+ .AXIM2_secondary_base = 0x00000000,
+ .AXIM_data_width = 0x00000100,
+ .l1d_ways = 0x00000008,
+ .l1i_ways = 0x00000004,
+ .l2way_num = 0x00000008,
+ .dma_jtlb_entries = 0x00000040,
+ },
+};
diff --git a/include/hw/hexagon/hexagon.h b/include/hw/hexagon/hexagon.h
index 3d7b3cb12d..62398eeb35 100644
--- a/include/hw/hexagon/hexagon.h
+++ b/include/hw/hexagon/hexagon.h
@@ -27,6 +27,8 @@ typedef enum {
v71_rev = 0x8c71,
v73_rev = 0x8c73,
v73m_rev = 0xcc73,
+ v81_rev = 0x8781,
+ v81dgb_1_rev = 0xcc81,
} Rev_t;
#define HEXAGON_LATEST_REV v73
#define HEXAGON_LATEST_REV_UPPER V73
@@ -129,6 +131,15 @@ union hexagon_config_table {
uint32_t corecfg_present;
uint32_t coproc2_fp16_acc_exp;
uint32_t AXIM2_secondary_base;
+ uint32_t AXIM_data_width;
+ /* Number of L1 data cache ways */
+ uint32_t l1d_ways;
+ /* Number of L1 instruction cache ways */
+ uint32_t l1i_ways;
+ /* Number of L2 cache ways */
+ uint32_t l2way_num;
+ /* Number of DMA JTLB entries */
+ uint32_t dma_jtlb_entries;
};
uint32_t raw[HEXAGON_CFGSPACE_ENTRIES];
};
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 8a4a81dc26..719979d6c3 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -50,7 +50,7 @@ typedef struct HexagonGlobalRegState HexagonGlobalRegState;
#define PRED_WRITES_MAX 5 /* 4 insns + endloop */
#define VSTORES_MAX 2
#define MAX_TLB_ENTRIES 1024
-#define THREADS_MAX 8
+#define THREADS_MAX 16
#define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU
#ifndef CONFIG_USER_ONLY