Commit 78f51b0ea5 for qemu.org

commit 78f51b0ea5205bda472652b326caf439d92a2c3b
Author: Richard Henderson <richard.henderson@linaro.org>
Date:   Wed Aug 12 15:31:27 2026 -0700

    disas/riscv: Reject all of OP-32 and OP-IMM-32 for RV32

    These entire base opcodes are RV64.  Reject them all at once
    rather than one at a time.

    Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
    Message-ID: <20260812223142.349142-38-richard.henderson@linaro.org>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/disas/riscv.c b/disas/riscv.c
index 75c2fa11e6..e650ad7688 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -3311,6 +3311,10 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
             }
             break;
         case 6:
+            /* OP-IMM-32 */
+            if (isa == rv32) {
+                break;
+            }
             switch ((inst >> 12) & 0b111) {
             case 0: op = rv_op_addiw; break;
             case 1:
@@ -3557,6 +3561,10 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
             break;
         case 13: op = rv_op_lui; break;
         case 14:
+            /* OP-32 */
+            if (isa == rv32) {
+                break;
+            }
             switch (((inst >> 22) & 0b1111111000) |
                     ((inst >> 12) & 0b0000000111)) {
             case 0: op = rv_op_addw; break;