Commit 85d38315fd for qemu.org
commit 85d38315fd19cda7fcfec5350f27cdfa15742600
Author: Christian S. Lima <christianslima@proton.me>
Date: Sat Aug 8 03:18:54 2026 +0000
target/riscv/tcg: sret in virtual user mode raises virtual instruction exception
Currently, when a `sret` is executed in virtual user mode, qemu
raise an `illegal instruction exception`, but in this case the correct
behavior is to raise a `virtual instruction exception` and the code
already contains a check to it, but it's not enough to catch. This
patch is useful to improve the correctness of the virtualization of
the risc v architecture.
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3622
Signed-off-by: Christian S. Lima <christianslima@proton.me>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20260808031849.59726-1-christianslima@proton.me>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c
index a7bd42d2c6..3e94005d2b 100644
--- a/target/riscv/tcg/op_helper.c
+++ b/target/riscv/tcg/op_helper.c
@@ -308,6 +308,11 @@ target_ulong helper_sret(CPURISCVState *env)
const privilege_mode_t src_priv = env->priv;
const bool src_virt = env->virt_enabled;
+ if ((env->virt_enabled && env->priv < PRV_S) ||
+ (env->virt_enabled && get_field(env->hstatus, HSTATUS_VTSR))) {
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+ }
+
if (!(env->priv >= PRV_S)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
@@ -323,10 +328,6 @@ target_ulong helper_sret(CPURISCVState *env)
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
- if (env->virt_enabled && get_field(env->hstatus, HSTATUS_VTSR)) {
- riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
- }
-
mstatus = env->mstatus;
prev_priv = get_field(mstatus, MSTATUS_SPP);
mstatus = set_field(mstatus, MSTATUS_SIE,