Commit 899ffd0113 for qemu.org

commit 899ffd01131b42cd45de4f8c72f912589f502f9a
Author: Alex Bennée <alex.bennee@linaro.org>
Date:   Wed Apr 22 13:52:25 2026 +0100

    target/arm: migrate BXJ trap syndromes to registerfields

    This is an Armv7 specific syndrome for chips with Jazelle
    functionality.

    Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
    Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
    Message-id: 20260422125250.1303100-9-alex.bennee@linaro.org
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index 52a6745cb2..6fcf0ac757 100644
--- a/target/arm/syndrome.h
+++ b/target/arm/syndrome.h
@@ -440,10 +440,26 @@ static inline uint32_t syn_btitrap(int btype)
     return res;
 }

+/*
+ * ISS encoding for trapped BXJ execution
+ *
+ * This is an Armv7 encoding.
+ */
+FIELD(BXJ_ISS, RM, 0, 4)
+/* bits 4:19 are Reserved, UNK/SBZP */
+FIELD(BXJ_ISS, COND, 20, 4)
+FIELD(BXJ_ISS, CV, 24, 1)
+
 static inline uint32_t syn_bxjtrap(int cv, int cond, int rm)
 {
-    return (EC_BXJTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL |
-        (cv << 24) | (cond << 20) | rm;
+    uint32_t res = syn_set_ec(0, EC_BXJTRAP);
+    res = FIELD_DP32(res, SYNDROME, IL, 1);
+
+    res = FIELD_DP32(res, BXJ_ISS, CV, cv);
+    res = FIELD_DP32(res, BXJ_ISS, COND, cond);
+    res = FIELD_DP32(res, BXJ_ISS, RM, rm);
+
+    return res;
 }

 static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, int vncr,