Commit 90789a83fb for qemu.org
commit 90789a83fb8b608f08a2716a3517c5ad743b3823
Author: Richard Henderson <richard.henderson@linaro.org>
Date: Wed Aug 26 10:42:12 2026 -0700
target/arm: Enable FEAT_SVE_AES2 for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260826174213.614571-26-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index e3ec4b6137..34b63f9867 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -199,6 +199,7 @@ the following architecture extensions:
- FEAT_SSVE_FP8FMA (SVE2 FP8 multiply-accumulate to half-precision and single-precision instructions in Streaming SVE mode)
- FEAT_SVE (Scalable Vector Extension)
- FEAT_SVE_AES (Scalable Vector AES instructions)
+- FEAT_SVE_AES2 (SVE multi-vector Advanced Encryption Standard and 128-bit polynomial multiply long instructions)
- FEAT_SVE_B16B16 (Non-widening BFloat16 arithmetic for SVE2)
- FEAT_SVE_BFSCALE (BFloat16 Floating-Point Adjust Exponent)
- FEAT_SVE_BitPerm (Scalable Vector Bit Permutes instructions)
diff --git a/linux-user/aarch64/elfload.c b/linux-user/aarch64/elfload.c
index 4359312ee3..f87f22f690 100644
--- a/linux-user/aarch64/elfload.c
+++ b/linux-user/aarch64/elfload.c
@@ -182,6 +182,7 @@ abi_ulong get_elf_hwcap(CPUState *cs)
GET_FEATURE_ID(aa64_sme2p2, ARM_HWCAP_A64_SME2P2);
GET_FEATURE_ID(aa64_sve_bfscale, ARM_HWCAP_A64_SVE_BFSCALE);
GET_FEATURE_ID(aa64_ssve_bitperm, ARM_HWCAP_A64_SME_SBITPERM);
+ GET_FEATURE_ID(aa64_sve_aes2, ARM_HWCAP_A64_SVE_AES2);
return hwcaps;
}
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 4994a87afe..affd87a3ae 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1471,7 +1471,7 @@ void aarch64_max_v9_tcg_initfn(Object *obj)
t = GET_IDREG(isar, ID_AA64ZFR0);
t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 3); /* v9.4: FEAT_SVE2p2 */
- t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* v9.0: FEAT_SVE_PMULL128 */
+ t = FIELD_DP64(t, ID_AA64ZFR0, AES, 3); /* v9.5: FEAT_SVE_AES2 */
t = FIELD_DP64(t, ID_AA64ZFR0, ELTPERM, 1); /* v9.4: FEAT_SVE2p2 */
t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* v9.0: FEAT_SVE_BitPerm */
t = FIELD_DP64(t, ID_AA64ZFR0, B16B16, 2); /* v9.2: FEAT_SVE_BFSCALE */