Commit 9b3e7f881b for qemu.org

commit 9b3e7f881b63415344018b8ef9077e47c8ccea50
Author: Richard Henderson <richard.henderson@linaro.org>
Date:   Thu Aug 6 10:27:09 2026 -0700

    target/arm: Enable FEAT_FGWTE3 for -cpu max

    Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
    Message-id: 20260806172709.333300-7-richard.henderson@linaro.org
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index ff02435975..e342ebb444 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -78,6 +78,7 @@ the following architecture extensions:
 - FEAT_FAMINMAX (Floating-point maximum and minimum absolute value instructions)
 - FEAT_FCMA (Floating-point complex number instructions)
 - FEAT_FGT (Fine-Grained Traps)
+- FEAT_FGWTE3 (Fine-Grained Write Trap EL3)
 - FEAT_FHM (Floating-point half-precision multiplication instructions)
 - FEAT_FP (Floating Point extensions)
 - FEAT_FP16 (Half-precision floating-point data processing)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 251c4b3cf6..2d48b736bc 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1466,6 +1466,7 @@ void aarch64_max_v9_tcg_initfn(Object *obj)

     t = GET_IDREG(isar, ID_AA64MMFR4);
     t = FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1);    /* v9.4: FEAT_ASID2 */
+    t = FIELD_DP64(t, ID_AA64MMFR4, FGWTE3, 1);   /* v9.4: FEAT_FGWTE3 */
     SET_IDREG(isar, ID_AA64MMFR4, t);

     t = GET_IDREG(isar, ID_AA64ZFR0);