Commit 9c93f9e5ed for qemu.org
commit 9c93f9e5ed9e8001d1e65b0d7ce75e82a6ff7bab
Author: Bibo Mao <maobibo@loongson.cn>
Date: Fri Jun 5 16:25:46 2026 +0800
target/loongarch: Use sys_state in csr_helper.c when accessing CSR registers
When accessing CSR registers in file csr_helper.c, use sys_state rather
than env. There is no function change.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@mailo.com>
Tested-by: Song Gao <gaosong@loongson.cn>
Message-ID: <20260605082552.175336-9-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_helper.c
index cd35ca93c7..7dc33bc180 100644
--- a/target/loongarch/tcg/csr_helper.c
+++ b/target/loongarch/tcg/csr_helper.c
@@ -20,7 +20,8 @@
target_ulong helper_csrwr_stlbps(CPULoongArchState *env, target_ulong val)
{
- int64_t old_v = env->CSR_STLBPS;
+ CPUSysState *sys = env_sys(env);
+ int64_t old_v = sys->CSR_STLBPS;
/*
* The real hardware only supports the min tlb_ps is 12
@@ -33,7 +34,7 @@ target_ulong helper_csrwr_stlbps(CPULoongArchState *env, target_ulong val)
} else {
/* Only update PS field, reserved bit keeps zero */
val = FIELD_DP64(val, CSR_STLBPS, RESERVE, 0);
- env->CSR_STLBPS = val;
+ sys->CSR_STLBPS = val;
}
return old_v;
@@ -42,17 +43,18 @@ target_ulong helper_csrwr_stlbps(CPULoongArchState *env, target_ulong val)
target_ulong helper_csrrd_pgd(CPULoongArchState *env)
{
int64_t v;
+ CPUSysState *sys = env_sys(env);
- if (env->CSR_TLBRERA & 0x1) {
- v = env->CSR_TLBRBADV;
+ if (sys->CSR_TLBRERA & 0x1) {
+ v = sys->CSR_TLBRBADV;
} else {
- v = env->CSR_BADV;
+ v = sys->CSR_BADV;
}
if ((v >> 63) & 0x1) {
- v = env->CSR_PGDH;
+ v = sys->CSR_PGDH;
} else {
- v = env->CSR_PGDL;
+ v = sys->CSR_PGDL;
}
return v;
@@ -61,10 +63,11 @@ target_ulong helper_csrrd_pgd(CPULoongArchState *env)
target_ulong helper_csrrd_cpuid(CPULoongArchState *env)
{
LoongArchCPU *lac = env_archcpu(env);
+ CPUSysState *sys = env_sys(env);
- env->CSR_CPUID = CPU(lac)->cpu_index;
+ sys->CSR_CPUID = CPU(lac)->cpu_index;
- return env->CSR_CPUID;
+ return sys->CSR_CPUID;
}
target_ulong helper_csrrd_tval(CPULoongArchState *env)
@@ -77,16 +80,17 @@ target_ulong helper_csrrd_tval(CPULoongArchState *env)
target_ulong helper_csrrd_msgir(CPULoongArchState *env)
{
int irq, new;
+ CPUSysState *sys = env_sys(env);
- irq = find_first_bit((unsigned long *)env->CSR_MSGIS, 256);
+ irq = find_first_bit((unsigned long *)sys->CSR_MSGIS, 256);
if (irq < 256) {
- clear_bit(irq, (unsigned long *)env->CSR_MSGIS);
- new = find_first_bit((unsigned long *)env->CSR_MSGIS, 256);
+ clear_bit(irq, (unsigned long *)sys->CSR_MSGIS);
+ new = find_first_bit((unsigned long *)sys->CSR_MSGIS, 256);
if (new < 256) {
return irq;
}
- env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, MSGINT, 0);
+ sys->CSR_ESTAT = FIELD_DP64(sys->CSR_ESTAT, CSR_ESTAT, MSGINT, 0);
} else {
/* bit 31 set 1 for no invalid irq */
irq = BIT(31);
@@ -97,21 +101,23 @@ target_ulong helper_csrrd_msgir(CPULoongArchState *env)
target_ulong helper_csrwr_estat(CPULoongArchState *env, target_ulong val)
{
- int64_t old_v = env->CSR_ESTAT;
+ CPUSysState *sys = env_sys(env);
+ int64_t old_v = sys->CSR_ESTAT;
/* Only IS[1:0] can be written */
- env->CSR_ESTAT = deposit64(env->CSR_ESTAT, 0, 2, val);
+ sys->CSR_ESTAT = deposit64(sys->CSR_ESTAT, 0, 2, val);
return old_v;
}
target_ulong helper_csrwr_asid(CPULoongArchState *env, target_ulong val)
{
- int64_t old_v = env->CSR_ASID;
+ CPUSysState *sys = env_sys(env);
+ int64_t old_v = sys->CSR_ASID;
/* Only ASID filed of CSR_ASID can be written */
- env->CSR_ASID = deposit64(env->CSR_ASID, 0, 10, val);
- if (old_v != env->CSR_ASID) {
+ sys->CSR_ASID = deposit64(sys->CSR_ASID, 0, 10, val);
+ if (old_v != sys->CSR_ASID) {
tlb_flush(env_cpu(env));
}
return old_v;
@@ -120,7 +126,8 @@ target_ulong helper_csrwr_asid(CPULoongArchState *env, target_ulong val)
target_ulong helper_csrwr_tcfg(CPULoongArchState *env, target_ulong val)
{
LoongArchCPU *cpu = env_archcpu(env);
- int64_t old_v = env->CSR_TCFG;
+ CPUSysState *sys = env_sys(env);
+ int64_t old_v = sys->CSR_TCFG;
cpu_loongarch_store_constant_timer_config(cpu, val);
@@ -143,7 +150,8 @@ target_ulong helper_csrwr_ticlr(CPULoongArchState *env, target_ulong val)
target_ulong helper_csrwr_pwcl(CPULoongArchState *env, target_ulong val)
{
uint8_t shift, ptbase;
- int64_t old_v = env->CSR_PWCL;
+ CPUSysState *sys = env_sys(env);
+ int64_t old_v = sys->CSR_PWCL;
/*
* The real hardware only supports 64bit PTE width now, 128bit or others
@@ -160,14 +168,15 @@ target_ulong helper_csrwr_pwcl(CPULoongArchState *env, target_ulong val)
qemu_log_mask(LOG_GUEST_ERROR,
"Attempted set ptbase 2^%d\n", ptbase);
}
- env->CSR_PWCL = val;
+ sys->CSR_PWCL = val;
return old_v;
}
target_ulong helper_csrwr_pwch(CPULoongArchState *env, target_ulong val)
{
uint8_t has_ptw;
- int64_t old_v = env->CSR_PWCH;
+ CPUSysState *sys = env_sys(env);
+ int64_t old_v = sys->CSR_PWCH;
val = FIELD_DP64(val, CSR_PWCH, RESERVE, 0);
has_ptw = FIELD_EX32(env->cpucfg[2], CPUCFG2, HPTW);
@@ -175,6 +184,6 @@ target_ulong helper_csrwr_pwch(CPULoongArchState *env, target_ulong val)
val = FIELD_DP64(val, CSR_PWCH, HPTW_EN, 0);
}
- env->CSR_PWCH = val;
+ sys->CSR_PWCH = val;
return old_v;
}