Commit a9779d24be for qemu.org

commit a9779d24be31338d90aa19a560e69cc4c9660627
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date:   Wed Aug 19 12:56:55 2026 +0200

    target/riscv: Allow UXL to be 3 in mstatus on rv128

    Valid UXL field values for mstatus were restricted to fix a
    reported issue, but this inadvertently broke the experimental
    rv128 support where a value of 3 validly represents 128-bit
    execution.

    Update the mstatus write logic to permit UXL=3 when running on
    an rv128 CPU.

    Fixes: dcd028517749 ("target/riscv: Apply UXL WARL handling to vsstatus")
    Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
    Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
    Reviewed-by: Chao Liu <chao.liu@processmission.com>
    Message-ID: <20260819105655.33391-3-frederic.petrot@univ-grenoble-alpes.fr>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
index 9cc6297328..4c8959a33d 100644
--- a/target/riscv/tcg/csr.c
+++ b/target/riscv/tcg/csr.c
@@ -2014,8 +2014,8 @@ static uint64_t riscv_write_uxl(CPURISCVState *env, uint64_t val,
     RISCVMXL xl = riscv_cpu_mxl(env);
     uint64_t uxl = get_field(val, field);

-    if (uxl == MXL_RV128) {
-        uxl = xl == MXL_RV128 ? MXL_RV64 : xl;
+    if (xl != MXL_RV128 && uxl == MXL_RV128) {
+        uxl = xl;
         val = set_field(val, field, uxl);
     }