Commit aa42300f86 for qemu.org

commit aa42300f86d172d7252f0cb95c2efd7570ad6b8f
Author: Peter Maydell <peter.maydell@linaro.org>
Date:   Thu May 21 13:29:12 2026 +0100

    target/arm: Use FPST_A64_F16 for SVE FCVTLT_hs

    We should be using the F16-specific float_status for conversions from
    half-precision, because halfprec inputs never set Input Denormal.  If
    we use the FPST_A64 fpstatus then we will incorrectly set FPCR.IDC
    for input-denormals when FPCR.AH=1.

    In commit e07b48995aaa we updated most of the halfprec-to-other
    conversion insns to use FPST_A64_F16 as part of implementing
    FEAT_AHP.  However we missed the SVE FCVTLT instruction, which has a
    halfprec-to-single encoding.

    Correct the FPST we use for the hs variant of FCVTLT.

    Cc: qemu-stable@nongnu.org
    Fixes: e07b48995aaa ("target/arm: Use FPST_A64_F16 for halfprec-to-other conversions")a
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
    Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
    Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
    Message-id: 20260521122913.1565011-3-peter.maydell@linaro.org

diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index bf9f0ae179..59b8c494a8 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -7827,7 +7827,7 @@ TRANS_FEAT(BFCVTNT, aa64_sme_sve_bf16, gen_gvec_fpst_arg_zpz,
            s->fpcr_ah ? FPST_AH : FPST_A64)

 TRANS_FEAT(FCVTLT_hs, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz,
-           gen_helper_sve2_fcvtlt_hs, a, 0, FPST_A64)
+           gen_helper_sve2_fcvtlt_hs, a, 0, FPST_A64_F16)
 TRANS_FEAT(FCVTLT_sd, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz,
            gen_helper_sve2_fcvtlt_sd, a, 0, FPST_A64)