Commit acb6d59857 for qemu.org
commit acb6d598578fbb47b687ec02a664919950e15fbd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: Fri May 1 14:19:04 2026 +1000
fpu: Introduce FloatSNaNRule
Merge snan_bit_is_one and no_signaling_nans into one control.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
index e2e3ec0e81..0b527302a5 100644
--- a/fpu/softfloat-specialize.c.inc
+++ b/fpu/softfloat-specialize.c.inc
@@ -79,26 +79,6 @@ this code that are retained.
* version 2 or later. See the COPYING file in the top-level directory.
*/
-/*
- * Define whether architecture deviates from IEEE in not supporting
- * signaling NaNs (so all NaNs are treated as quiet).
- */
-static inline bool no_signaling_nans(float_status *status)
-{
- return status->no_signaling_nans;
-}
-
-/* Define how the architecture discriminates signaling NaNs.
- * This done with the most significant bit of the fraction.
- * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008
- * the msb must be zero. MIPS is (so far) unique in supporting both the
- * 2008 revision and backward compatibility with their original choice.
- */
-static inline bool snan_bit_is_one(float_status *status)
-{
- return status->snan_bit_is_one;
-}
-
/*----------------------------------------------------------------------------
| For the deconstructed floating-point with fraction FRAC, return true
| if the fraction represents a signalling NaN; otherwise false.
@@ -106,11 +86,15 @@ static inline bool snan_bit_is_one(float_status *status)
static bool frac_msb_is_snan(bool msb, float_status *status)
{
- if (no_signaling_nans(status)) {
+ switch (get_snan_rule(status)) {
+ case float_snan_never:
return false;
- } else {
- return msb == snan_bit_is_one(status);
+ case float_snan_bit_is_one:
+ return msb;
+ case float_snan_bit_is_zero:
+ return !msb;
}
+ g_assert_not_reached();
}
static bool parts_is_snan_frac(uint64_t frac, float_status *status)
@@ -172,14 +156,18 @@ FloatParts128 parts128_default_nan(float_status *status)
static uint64_t parts_silence_nan_frac(uint64_t frac, float_status *status)
{
- g_assert(!no_signaling_nans(status));
-
- /* The only snan_bit_is_one target without default_nan_mode is HPPA. */
- if (snan_bit_is_one(status)) {
+ switch (get_snan_rule(status)) {
+ case float_snan_bit_is_zero:
+ frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1);
+ break;
+ case float_snan_bit_is_one:
+ /* The only snan_bit_is_one target without default_nan_mode is HPPA. */
frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1));
frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2);
- } else {
- frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1);
+ break;
+ case float_snan_never:
+ default:
+ g_assert_not_reached();
}
return frac;
}
@@ -390,7 +378,7 @@ bool floatx80_is_signaling_nan(floatx80 a, float_status *status)
floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
{
/* None of the targets that have snan_bit_is_one use floatx80. */
- assert(!snan_bit_is_one(status));
+ assert(get_snan_rule(status) == float_snan_bit_is_zero);
a.low |= UINT64_C(0xC000000000000000);
return a;
}
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
index 745a49f07a..95edd22842 100644
--- a/include/fpu/softfloat-helpers.h
+++ b/include/fpu/softfloat-helpers.h
@@ -127,14 +127,9 @@ static inline void set_default_nan_mode(bool val, float_status *status)
status->default_nan_mode = val;
}
-static inline void set_snan_bit_is_one(bool val, float_status *status)
+static inline void set_snan_rule(FloatSNaNRule val, float_status *status)
{
- status->snan_bit_is_one = val;
-}
-
-static inline void set_no_signaling_nans(bool val, float_status *status)
-{
- status->no_signaling_nans = val;
+ status->float_snan_rule = val;
}
static inline bool get_float_detect_tininess(const float_status *status)
@@ -203,6 +198,11 @@ static inline bool get_default_nan_mode(const float_status *status)
return status->default_nan_mode;
}
+static inline FloatSNaNRule get_snan_rule(float_status *status)
+{
+ return status->float_snan_rule;
+}
+
static inline FloatFTZDetection get_float_ftz_detection(const float_status *status)
{
return status->ftz_detection;
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index 5048faa76f..cf7093fa86 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -192,6 +192,23 @@ typedef enum __attribute__((__packed__)) {
floatx80_precision_s,
} FloatX80RoundPrec;
+/*
+ * Define how the architecture discriminates signaling NaNs.
+ * This done with the most significant bit of the fraction.
+ *
+ * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008
+ * the msb must be 0. But setting the msb to 1 got baked into HPPA, SH4,
+ * and pre-2008 MIPS.
+ *
+ * Further, some architectures (or modes of architectures) do not detect
+ * signaling NaNs at all.
+ */
+typedef enum __attribute__((__packed__)) {
+ float_snan_bit_is_zero,
+ float_snan_bit_is_one,
+ float_snan_never,
+} FloatSNaNRule;
+
/*
* 2-input NaN propagation rule. Individual architectures have
* different rules for which input NaN is propagated to the output
@@ -394,6 +411,7 @@ typedef struct float_status {
Float2NaNPropRule float_2nan_prop_rule;
Float3NaNPropRule float_3nan_prop_rule;
FloatInfZeroNaNRule float_infzeronan_rule;
+ FloatSNaNRule float_snan_rule;
bool tininess_before_rounding;
/* should denormalised results go to zero and set output_denormal_flushed? */
bool flush_to_zero;
@@ -412,13 +430,6 @@ typedef struct float_status {
* create a default NaN.
*/
uint8_t default_nan_pattern;
- /*
- * The flags below are not used on all specializations and may
- * constant fold away (see snan_bit_is_one()/no_signalling_nans() in
- * softfloat-specialize.inc.c)
- */
- bool snan_bit_is_one;
- bool no_signaling_nans;
/* should overflowed results subtract re_bias to its exponent? */
bool rebias_overflow;
/* should underflowed results add re_bias to its exponent? */
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
index 2d272730f6..cdbebcfeb3 100644
--- a/target/hppa/fpu_helper.c
+++ b/target/hppa/fpu_helper.c
@@ -66,7 +66,7 @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
/* Default NaN: sign bit clear, msb-1 frac bit set */
set_float_default_nan_pattern(0b00100000, &env->fp_status);
- set_snan_bit_is_one(true, &env->fp_status);
+ set_snan_rule(float_snan_bit_is_one, &env->fp_status);
/*
* "PA-RISC 2.0 Architecture" says it is IMPDEF whether the flushing
* enabled by FPSR.D happens before or after rounding. We pick "before"
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
index 08fb409390..cf667c6637 100644
--- a/target/mips/fpu_helper.h
+++ b/target/mips/fpu_helper.h
@@ -35,7 +35,8 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
* With nan2008, SNaNs are silenced in the usual way.
* Before that, SNaNs are not silenced; default nans are produced.
*/
- set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status);
+ set_snan_rule(nan2008 ? float_snan_bit_is_zero : float_snan_bit_is_one,
+ &env->active_fpu.fp_status);
set_default_nan_mode(!nan2008, &env->active_fpu.fp_status);
/*
* For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
diff --git a/target/mips/msa.c b/target/mips/msa.c
index 32c6acbcc5..53fbce10d3 100644
--- a/target/mips/msa.c
+++ b/target/mips/msa.c
@@ -84,8 +84,8 @@ void msa_reset(CPUMIPSState *env)
/* clear float_status nan mode */
set_default_nan_mode(0, &env->active_tc.msa_fp_status);
- /* set proper signanling bit meaning ("1" means "quiet") */
- set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
+ /* set proper signanling bit meaning */
+ set_snan_rule(float_snan_bit_is_zero, &env->active_tc.msa_fp_status);
/* Inf * 0 + NaN returns the input NaN */
set_float_infzeronan_rule(float_infzeronan_dnan_never,
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 40d5fde76d..763424695c 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -151,7 +151,7 @@ static void superh_cpu_reset_hold(Object *obj, ResetType type)
set_flush_to_zero(1, &env->fp_status);
#endif
set_default_nan_mode(1, &env->fp_status);
- set_snan_bit_is_one(true, &env->fp_status);
+ set_snan_rule(float_snan_bit_is_one, &env->fp_status);
/* sign bit clear, set all frac bits other than msb */
set_float_default_nan_pattern(0b00111111, &env->fp_status);
/*
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index d6d42319e5..2015a4e3d0 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -209,7 +209,8 @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
#endif
/* For inf * 0 + NaN, return the input NaN */
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
- set_no_signaling_nans(!dfpu, &env->fp_status);
+ set_snan_rule(dfpu ? float_snan_bit_is_zero : float_snan_never,
+ &env->fp_status);
/* Default NaN value: sign bit clear, set frac msb */
set_float_default_nan_pattern(0b01000000, &env->fp_status);
xtensa_use_first_nan(env, !dfpu);