Commit af15801a61 for qemu.org

commit af15801a61d66510434131ae50c2ad2135fa3de1
Author: Tao Tang <tangtao1634@phytium.com.cn>
Date:   Wed Mar 4 22:23:43 2026 +0800

    hw/arm/smmuv3: Correct SMMUEN field name in CR0

    The FIELD macro for the SMMU enable bit in the CR0 register was
    incorrectly named SMMU_ENABLE.

    The ARM SMMUv3 Architecture Specification (both older IHI 0070.E.a and
    newer IHI 0070.G.b) consistently refers to the SMMU enable bit as SMMUEN.

    This change makes our implementation consistent with the manual.

    Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn>
    Reviewed-by: Eric Auger <eric.auger@redhat.com>
    Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
    Reviewed-by: Mostafa Saleh <smostafa@google.com>
    Message-id: 20260304142344.3341444-3-tangtao1634@phytium.com.cn
    Fixes: 10a83cb9887 ("hw/arm/smmuv3: Skeleton")
    Link: https://lists.nongnu.org/archive/html/qemu-arm/2025-09/msg01270.html
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index b666109ad9..eb482c7000 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -41,7 +41,7 @@ typedef enum SMMUTranslationClass {

 static inline int smmu_enabled(SMMUv3State *s)
 {
-    return FIELD_EX32(s->cr[0], CR0, SMMU_ENABLE);
+    return FIELD_EX32(s->cr[0], CR0, SMMUEN);
 }

 /* Command Queue Entry */
diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h
index 2df54ba60f..9f78bbe89e 100644
--- a/include/hw/arm/smmuv3-common.h
+++ b/include/hw/arm/smmuv3-common.h
@@ -351,7 +351,7 @@ REG32(IDR5,                0x14)
 REG32(IIDR,                0x18)
 REG32(AIDR,                0x1c)
 REG32(CR0,                 0x20)
-    FIELD(CR0, SMMU_ENABLE,   0, 1)
+    FIELD(CR0, SMMUEN,   0, 1)
     FIELD(CR0, EVENTQEN,      2, 1)
     FIELD(CR0, CMDQEN,        3, 1)