Commit af1e669cef for qemu.org

commit af1e669cef162e8d9b5f2f176e8b909d61c4b530
Author: wangyang <wangyang25@otcaix.iscas.ac.cn>
Date:   Thu Aug 13 18:39:06 2026 +0800

    target/riscv: reject FMV.X.W/FMV.W.X under Zfinx

    Zfinx explicitly excludes the FMV transfer instructions, but
    trans_fmv_x_w/trans_fmv_w_x used REQUIRE_ZFINX_OR_F so a Zfinx-only
    CPU accepted them.  Require RVF instead so the transfers trap with
    an illegal instruction when only Zfinx is present.

    Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4108
    Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
    Signed-off-by: wangyang <wangyang25@otcaix.iscas.ac.cn>
    Message-ID: <36c7cfebd27b4b6e8bcdd00e09e9dda0@wangyang25.otcaix.iscas.ac.cn>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/target/riscv/tcg/insn_trans/trans_rvf.c.inc b/target/riscv/tcg/insn_trans/trans_rvf.c.inc
index 481f7282da..636dec1664 100644
--- a/target/riscv/tcg/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/tcg/insn_trans/trans_rvf.c.inc
@@ -434,7 +434,8 @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
 {
     /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */
     REQUIRE_FPU;
-    REQUIRE_ZFINX_OR_F(ctx);
+    /* Zfinx explicitly excludes the FMV transfer instructions. */
+    REQUIRE_EXT(ctx, RVF);

     TCGv dest = dest_gpr(ctx, a->rd);
     TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
@@ -537,7 +538,8 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
 {
     /* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */
     REQUIRE_FPU;
-    REQUIRE_ZFINX_OR_F(ctx);
+    /* Zfinx explicitly excludes the FMV transfer instructions. */
+    REQUIRE_EXT(ctx, RVF);

     TCGv_i64 dest = dest_fpr(ctx, a->rd);
     TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);