Commit af37cd2821 for qemu.org

commit af37cd2821f970a1a9d2d34fa0d319f80d2ab84d
Author: Vladimir Isaev <vvisaev@gmail.com>
Date:   Mon Aug 17 18:06:37 2026 +0300

    riscv: csr: do not drop C bit on misa write

    According to spec:
    > Writing misa may increase IALIGN, e.g., by disabling the "C" extension.
    > If an instruction that would write misa increases IALIGN, and the
    > subsequent instruction’s address is not IALIGN-bit aligned, the
    > write to misa is suppressed, leaving misa unchanged.

    So attempt to disable C extension if next instruction is not aligned should not
    change the misa.

    Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
    Signed-off-by: Vladimir Isaev <vvisaev@gmail.com>
    Reviewed-by: Chao Liu <chao.liu@processmission.com>
    Message-ID: <20260817150653.40357-2-vvisaev@gmail.com>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
index 4c8959a33d..002f7e69c1 100644
--- a/target/riscv/tcg/csr.c
+++ b/target/riscv/tcg/csr.c
@@ -2187,9 +2187,13 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
     /* Mask extensions that are not supported by this hart */
     val &= env->misa_ext_mask;

-    /* Suppress 'C' if next instruction is not aligned. */
-    if ((val & RVC) && (get_next_pc(env, ra) & 3) != 0) {
-        val &= ~RVC;
+    /* drop write if RVC is cleared and next instruction is not aligned */
+    if ((env->misa_ext & RVC) && !(val & RVC) &&
+         (get_next_pc(env, ra) & 3) != 0) {
+        qemu_log_mask(LOG_GUEST_ERROR, "Unable to write MISA ext value "
+                      "0x%x, MISA.C disable failed\n", env->misa_ext);
+
+        return RISCV_EXCP_NONE;
     }

     /* Disable RVG if any of its dependencies are disabled */