Commit b21adc910a for qemu.org
commit b21adc910a4d223de8189378262a92bb7682b839
Merge: 10a9fa0065 c45b02cb24
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: Thu Jun 11 13:22:33 2026 -0400
Merge tag 'pull-target-arm-20260610' of https://gitlab.com/pm215/qemu into staging
target-arm queue:
* Emulate various FP8 related features: FEAT_F8F16MM, FEAT_F8F32MM,
FEAT_FP8DOT2, FEAT_SSVE_FP8DOT2, FEAT_FP8DOT4, FEAT_SSVE_FP8DOT4,
FEAT_FP8FMA, FEAT_SSVE_FP8FMA, FEAT_SME_LUTv2, FEAT_FP8, FEAT_LUT
* Emulate MTE4 features: FEAT_MTE_CANONICAL_TAGS,
FEAT_MTE_NO_ADDRESS_TAGS, FEAT_MTE_PERM,FEAT_MTE_STORE_ONLY,
FEAT_MTE_TAGGED_FAR
* target/arm: fix WFET typo in syndrome
* target/arm: Preparatory patches for implementing WFE
* hw/dma/pl080: Don't use hw_error() for unimplemented features
* hw/intc/exynos4210_combiner: Avoid hw_error for guest errors
* hw/usb/hcd-ohci: Clean up USBPacket before freeing ISO TD packet
* hw/core/qdev-clock: Fix potential null pointer dereference
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# gpg: Signature made Wed 10 Jun 2026 11:58:17 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20260610' of https://gitlab.com/pm215/qemu: (71 commits)
target/arm: Enable FEAT_F8F16MM for -cpu max
target/arm: Implement FMMLA (FP8 to FP16) for SVE
target/arm: Implement FMMLA (FP8 to FP16) for AdvSIMD
target/arm: Enable FEAT_F8F32MM for -cpu max
target/arm: Implement FMMLA (FP8 to FP32) for SVE
target/arm: Implement FMMLA (FP8 to FP32) for AdvSIMD
target/arm: Enable FEAT_FP8DOT2, FEAT_SSVE_FP8DOT2 for -cpu max
target/arm: Implement FDOT (FP8 to FP16) for SVE
target/arm: Implement FDOT (FP8 to FP16) for AdvSIMD
target/arm: Enable FEAT_FP8DOT4, FEAT_SSVE_FP8DOT4 for -cpu max
target/arm: Implement FDOT (FP8 to FP32) for SVE
target/arm: Implement FDOT (FP8 to FP32) for AdvSIMD
target/arm: Enable FEAT_FP8FMA, FEAT_SSVE_FP8FMA for -cpu max
target/arm: Implement FMLALL{BB,BT,TB,TT} for SVE
target/arm: Implement FMLALL{BB, BT, TB, TT} for AdvSIMD
target/arm: Implement FMLALB, FMLALT (FP8 to FP16) for SVE
target/arm: Implement FMLALB, FMLALT for AdvSIMD
target/arm: Enable FEAT_SME_LUTv2 for -cpu max
target/arm: Implement LUTI4 (four registers, 8-bit)
target/arm: Implement MOVT (vector to table)
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>