Commit b3a977da8f for qemu.org

commit b3a977da8fc12f21f4674b433b9ff34d4ecb62ed
Author: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Date:   Mon Jul 27 10:28:46 2026 +0100

    target/arm: Only compile gicv5-cpuif.c when GICv5 is selected

    Only compile gicv5-cpuif.c when ARM_GICV5 is Kconfig-selected,
    otherwise we get when building with --without-default-devices:

      Undefined symbols for architecture arm64:
        "_gicv5_activate", referenced from:
            _gicr_cdia_read in target_arm_tcg_gicv5-cpuif.c.o
        "_gicv5_deactivate", referenced from:
            _gic_cddi_write in target_arm_tcg_gicv5-cpuif.c.o
        "_gicv5_get_hppi", referenced from:
            _gic_hppi in target_arm_tcg_gicv5-cpuif.c.o
        "_gicv5_request_config", referenced from:
            _gic_cdrcfg_write in target_arm_tcg_gicv5-cpuif.c.o
        "_gicv5_set_enabled", referenced from:
            _gic_cddis_write in target_arm_tcg_gicv5-cpuif.c.o
            _gic_cden_write in target_arm_tcg_gicv5-cpuif.c.o
        "_gicv5_set_handling", referenced from:
            _gic_cdhm_write in target_arm_tcg_gicv5-cpuif.c.o
        "_gicv5_set_pending", referenced from:
            _gic_cdpend_write in target_arm_tcg_gicv5-cpuif.c.o
        "_gicv5_set_priority", referenced from:
            _gic_cdpri_write in target_arm_tcg_gicv5-cpuif.c.o
        "_gicv5_set_target", referenced from:
            _gic_cdaff_write in target_arm_tcg_gicv5-cpuif.c.o

    Fixes: ee0f1ce00db ("target/arm: GICv5 cpuif: Initial skeleton and GSB barrier insns")
    Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
    Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
    Message-id: 20260721122135.6288-4-philmd@oss.qualcomm.com
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index 227e674ae2..cbfac0036e 100644
--- a/target/arm/tcg/meson.build
+++ b/target/arm/tcg/meson.build
@@ -91,6 +91,9 @@ arm_common_system_ss.add(files(
   'tlb_helper.c',
   'tlb-insns.c',
 ))
+arm_common_system_ss.add(when: 'CONFIG_ARM_GICV5', if_true: files(
+  'gicv5-cpuif.c',
+))
 arm_user_ss.add(files(
   'tlb_helper.c',
 ))