Commit c2444a426e for qemu.org

commit c2444a426ecd0099bca88ebabd4d0a930ab57f2e
Merge: 3f89b5de5b 5505e1cd02
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date:   Wed May 27 14:45:33 2026 -0400

    Merge tag 'single-binary-20260527' of https://github.com/philmd/qemu into staging

    Various patches related to single binary effort:

    - Preparatory patches to build RISCV machines once
    - Build ARM machines once
    - Build ARM 'max' CPU once
    - Few MAINTAINERS updates

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    # gpg: Signature made Wed 27 May 2026 06:29:07 EDT
    # gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
    # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
    # Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

    * tag 'single-binary-20260527' of https://github.com/philmd/qemu: (32 commits)
      MAINTAINERS: Update PhilMD's email address
      MAINTAINERS: update qualcomm git tree URL
      MAINTAINERS: Remove PhilMD from firmware sections
      tests/tcg: Explicitly check for 64-bit z/Architecture
      target/arm: Build cpu-max.c once
      target/arm: Build cpu32-system.o as common object
      target/arm: Define 'max' CPU type in cpu-max.c
      target/arm: Re-use common aarch64_aa32_a57_init() helper
      target/arm: Factor aarch64_aa32_a57_init() out
      target/arm: Only set %kvm_target when KVM is enabled
      target/arm: Implement DBGDEVID* registers in max AArch32 CPU
      target/arm: Use make_ccsidr(LEGACY) in 32 bit 'max' CPU type
      target/arm: Extract common code related to 'max' CPU
      target/arm: Build cpu64.o as common object
      target/arm: Build gdbstub64.o as common object
      target/arm: Introduce common system/user meson source set
      hw/arm/meson: Remove now unused arm_ss[] source set
      hw/arm/aspeed: Build objects once
      hw/arm/aspeed: Do not realize 64-bit CPU types under QTest
      hw/arm/raspi: Build objects once
      ...

    Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>