Commit c2b46bc3a6 for qemu.org
commit c2b46bc3a6ff341e6bcdc738e5f6250fe0d1e03b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: Tue Jun 9 12:21:08 2026 -0700
target/arm: Implement FMMLA (FP8 to FP16) for SVE
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260609192110.752384-45-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 753799008c..9e70d30964 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -1728,6 +1728,11 @@ static inline bool isar_feature_aa64_sve2_f8mm8(const ARMISARegisters *id)
return isar_feature_aa64_sve2(id) && isar_feature_aa64_f8mm8(id);
}
+static inline bool isar_feature_aa64_sve2_f8mm4(const ARMISARegisters *id)
+{
+ return isar_feature_aa64_sve2(id) && isar_feature_aa64_f8mm4(id);
+}
+
static inline bool
isar_feature_aa64_sme2_or_sve2_faminmax(const ARMISARegisters *id)
{
diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode
index 6610432528..b53fe6a58f 100644
--- a/target/arm/tcg/sve.decode
+++ b/target/arm/tcg/sve.decode
@@ -1809,6 +1809,7 @@ FMMLA_s 01100100 10 1 ..... 111 001 ..... ..... @rda_rn_rm_ex esz=2
FMMLA_d 01100100 11 1 ..... 111 001 ..... ..... @rda_rn_rm_ex esz=3
FMMLA_sb 01100100 00 1 ..... 111 000 ..... ..... @rda_rn_rm_ex esz=2
+FMMLA_hb 01100100 01 1 ..... 111 000 ..... ..... @rda_rn_rm_ex esz=1
### SVE2 Memory Gather Load Group
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index f6705ee95d..a85558bdaa 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -8477,3 +8477,5 @@ static bool do_fmmla_fp8(DisasContext *s, arg_rrrr_esz *a,
TRANS_FEAT_NONSTREAMING(FMMLA_sb, aa64_sve2_f8mm8, do_fmmla_fp8, a,
gen_helper_gvec_fmmla_sb)
+TRANS_FEAT_NONSTREAMING(FMMLA_hb, aa64_sve2_f8mm4, do_fmmla_fp8, a,
+ gen_helper_gvec_fmmla_hb)