Commit c3d9cbb789 for qemu.org

commit c3d9cbb789f8beabcf1239d73b7fd9b5a1fbb2cd
Author: James Hilliard <james.hilliard1@gmail.com>
Date:   Fri May 8 10:51:40 2026 +0200

    target/mips: add Octeon SAAD instruction

    SAAD is the doubleword form of SAA: it atomically adds rt to the
    naturally aligned 64-bit doubleword at base and discards the old memory
    value.

    Route it through the common SAA/SAAD translator so the MemOp selects the
    aligned doubleword transaction size.

    Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
    Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
    Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
    Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
    Message-Id: <20260520172313.23777-15-philmd@linaro.org>

diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode
index d6b241de42..d77717cd50 100644
--- a/target/mips/tcg/octeon.decode
+++ b/target/mips/tcg/octeon.decode
@@ -47,6 +47,7 @@ SNEI         011100 rs:5 rt:5 imm:s10 101111 &cmpi
 &saa         base rt
 @saa         ...... base:5 rt:5 ................ &saa
 SAA          011100 ..... ..... 00000 00000 011000 @saa
+SAAD         011100 ..... ..... 00000 00000 011001 @saa

 &lx          base index rd
 @lx          ...... base:5 index:5 rd:5 ...... ..... &lx
diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c
index 33b45611f2..23748695a1 100644
--- a/target/mips/tcg/octeon_translate.c
+++ b/target/mips/tcg/octeon_translate.c
@@ -183,3 +183,4 @@ static bool trans_saa(DisasContext *ctx, arg_saa *a, MemOp mop)
 }

 TRANS(SAA,  trans_saa, MO_32);
+TRANS(SAAD, trans_saa, MO_64);