Commit c4580a3a6d for qemu.org

commit c4580a3a6d1cc542479602048d15556a18928a22
Author: botszhuang <huang.botsz@gmail.com>
Date:   Fri Jul 24 20:42:20 2026 +0800

    hw/i2c/bcm2835_i2c: Correct CLKT register offset

    The Clock Stretch Timeout (CLKT) register for the BCM2835 I2C
    controller is actually located at offset 0x1c, not 0x20.

    Update the BCM2835_I2C_CLKT macro to match the hardware
    specification.

    Since QEMU's implementation ignores whatever value the guest
    writes to this register, and Linux only writes to CLKT and
    doesn't read it back, the main effect of this fix is to
    avoid an incorrect GUEST_ERROR log.

    Cc: qemu-stable@nongnu.org
    Fixes: 9cf3bc65afdb63 ("hw/i2c: Implement Broadcom Serial Controller (BSC)")
    Signed-off-by: botszhuang <botszhuang@gmail.com>
    Tested-by: Nick Huang <sef1548@gmail.com>
    Message-id: 20260724124220.24152-1-22925483+botszhuang@users.noreply.github.com
    [PMM: removed commit message paragraph about effects which I think
     is incorrect, substituted a different one]
    Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

diff --git a/include/hw/i2c/bcm2835_i2c.h b/include/hw/i2c/bcm2835_i2c.h
index 45f876df22..519c65f765 100644
--- a/include/hw/i2c/bcm2835_i2c.h
+++ b/include/hw/i2c/bcm2835_i2c.h
@@ -38,7 +38,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(BCM2835I2CState, BCM2835_I2C)
 #define BCM2835_I2C_FIFO    0x10                  /* FIFO */
 #define BCM2835_I2C_DIV     0x14                  /* Clock Divider */
 #define BCM2835_I2C_DEL     0x18                  /* Data Delay */
-#define BCM2835_I2C_CLKT    0x20                  /* Clock Stretch Timeout */
+#define BCM2835_I2C_CLKT    0x1c                  /* Clock Stretch Timeout */

 #define BCM2835_I2C_C_I2CEN     BIT(15)           /* I2C enable */
 #define BCM2835_I2C_C_INTR      BIT(10)           /* Interrupt on RXR */