Commit c7d073cf36 for qemu.org
commit c7d073cf3682a9a18cd0a0342a2340d7f33dcec4
Merge: 7332db732e 8acc03787b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: Fri Sep 11 09:15:50 2026 -1000
Merge tag 'pull-hex-20260911' of https://github.com/qualcomm/qemu into staging
Hexagon: v81 support
Initial support for v81, scalar only for now. HVX support
to follow.
Adds new machine definitions, v81 system architecture changes,
new scalar opcodes.
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# gpg: Signature made Fri 11 Sep 2026 06:02:37 AM HST
# gpg: using RSA key 3D66AAE474594824C88CE0F81A54AFB8E5646C32
# gpg: Good signature from "Brian Cain (OSS Qualcomm) <brian.cain@oss.qualcomm.com>" [unknown]
# gpg: aka "Brian Cain (QUIC) <quic_bcain@quicinc.com>" [unknown]
# gpg: aka "Brian Cain <bcain@kernel.org>" [unknown]
# gpg: aka "Brian Cain (QuIC) <bcain@quicinc.com>" [unknown]
# gpg: aka "Brian Cain (CAF) <bcain@codeaurora.org>" [unknown]
# gpg: aka "bcain" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6350 20F9 67A7 7164 79EF 49E0 175C 464E 541B 6D47
# Subkey fingerprint: 3D66 AAE4 7459 4824 C88C E0F8 1A54 AFB8 E564 6C32
* tag 'pull-hex-20260911' of https://github.com/qualcomm/qemu:
docs: Correct semihost spec URL
tests/functional: cover v81 system registers
target/hexagon: add v81 interrupt registers
target/hexagon: widen v81 CPU masks
hw/hexagon: move "sim" alias to "V81QA_1"
hw/hexagon: add the V81DGB_1 and V81QA_1 machines
target/hexagon: add Y2_tlbpp as unimplemented
target/hexagon: add the v79 instructions
target/hexagon: add the v73 J2_unpause scalar instruction
target/hexagon: add the v75, v79 and v81 CPU models
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>