Commit cf5dc5d019 for qemu.org

commit cf5dc5d019d8662ed9abe7b128b8dc3836b55b41
Author: Jon Kohler <jon@nutanix.com>
Date:   Thu Nov 6 10:46:21 2025 -0700

    target/i386: Add MSR_IA32_ARCH_CAPABILITIES ITS_NO

    Add bit definition for Indirect Target Selection (ITS_NO) bit 62, to
    allow ITS_NO to be added directly to a CPU model in the future.

    Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
    Signed-off-by: Jon Kohler <jon@nutanix.com>
    Link: https://lore.kernel.org/r/20251106174626.49930-2-jon@nutanix.com
    Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index c384302de3..f2679cc5b7 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1329,6 +1329,7 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
 #define MSR_ARCH_CAP_PBRSB_NO           (1U << 24)
 #define MSR_ARCH_CAP_GDS_NO             (1U << 26)
 #define MSR_ARCH_CAP_RFDS_NO            (1U << 27)
+#define MSR_ARCH_CAP_ITS_NO             (1U << 62)

 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT  (1U << 5)