Commit d0edff8ee1 for qemu.org
commit d0edff8ee17850d955c0b9724c296adcb9192c5c
Merge: 48560f0d96 3455eac92d
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: Mon Jul 6 18:37:28 2026 +0200
Merge tag 'pull-target-arm-20260706' of https://gitlab.com/pm215/qemu into staging
target-arm queue:
* hw/net/fsl_etsec: validate FCB offsets in process_tx_fcb()
* hw/arm/smmuv3-accel: Fix veventq read returning true on EAGAIN/EINTR
* target/arm: Only evaluate SCR_EL3.PIEN if ARM_FEATURE_EL3 is present
* hw/arm: use cortex-a9 mpcore base for CBAR on npcm7xx machines
* docs/specs/fw_cfg: Document all architecture register layouts
* hw/nvram/fw_cfg: Simplify functions so board models don't have
the opportunity to create non-standard fw_cfg register layouts
* hw/misc: use tracepoints rather than DPRINTF in imx ccm models
* hw/arm: add support for shim loading
* docs/system/arm: Document Zynq Buildroot boot
* target/arm: Report correct syndrome to AArch32 EL2 for trapped
Neon/VFP insns
* target/arm: implement WFET to not be a NOP
* target/arm: Emulate FEAT_SME_MOP4
* target/arm: Emulate FEAT_FPRCVT
* target/arm: Emulate FEAT_SSVE_FEXPA
# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmpLhTkZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3vssD/wOwsb9NZ4E7TfpK3JFl3WH
# ePkwg0dg/etzbMR+fQagij3oI0+1qFUn6qU5PJddAcP1Zwz8NouKJjfvJgnmAQoZ
# eIfoI29j1da6aOywicnKGlvjM3oEBZKxrC+ChJeF+8E0u1V0+msR9osluUa3ZNDf
# 4Zcik/h6hJxva8JMPjdds2ZJBDsVuLbNM6jBfbE3Bp7Lg7HZ48u6++YaZAFUFqHC
# gWHKs9jKAnzcL05cCLUU4LdyhJH1M3vLFnKbugn1zUlSb6L5oLrhCIIPKMcAuUjd
# 6OWOzVJEsooxf8iqvAcAFmXpZEzLal12zjYUPowCZGUzHx6kqBFfv7KoDMXKZXI9
# kYFhOsTmpWrE+VLT/ZwVExk/xdgUMlfyEy8aJzetexvaLIs7C7hWQH/FQn1h395Q
# ot79co3m6D3F11HQvSlJZthCZk0SE5A8hZQP8joPhSBJ3rM24nejINT5Lz6wbjm0
# ovMBjvBtvUiQm2KrqJ+dIFCOdabQXxnokDZSAxFUcPXd526MALyzhcR5Q5op9/OA
# 3A2KUOlkch4rdROifuRniN/UuN/oWHOkVzp7B/WOAn/KFVKFnuBwPcFvFfQjq81b
# G8RJ5jZyDmSLCf66pHT0xxC8cFhilwF56QxRH4vNPVbTvLdHgRHbJbF1f1hd1eMa
# Gy8zZGTXfo2hBz2qZmixfA==
# =NpV8
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 06 Jul 2026 12:36:41 CEST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20260706' of https://gitlab.com/pm215/qemu: (49 commits)
target/arm: Define fields for NSACR
target/arm: Report correct syndrome to AArch32 EL2 for trapped Neon/VFP insns
target/arm: Separate syndrome functions for A32 and A64
target/arm: Separate out Neon from VFP access checks
target/arm: Enable FEAT_SME_MOP4 for -cpu max
target/arm: Implement USMOP4[AS]
target/arm: Implement UMOP4[AS] (4-way)
target/arm: Implement UMOP4[AS] (2-way)
target/arm: Implement SUMOP4[AS]
target/arm: Implement SMOP4[AS] (4-way)
target/arm: Implement SMOP4[AS] (2-way)
target/arm: Implement FMOP4A (widening, 2-way, FP8 to FP16)
target/arm: Implement FMOP4 (widening, 4-way fp8 to fp32)
target/arm: Implement FMOP4 (widening, 2-way fp16 to fp32)
target/arm: Implement BFMOP4 (widening)
target/arm: Implement BFMOP4 (non-widening)
target/arm: Implement FMOP4 (non-widening) for float64
target/arm: Implement FMOP4 (non-widening) for float16
target/arm: Implement FMOP4 (non-widening) for float32
docs/system/arm: Document Zynq Buildroot boot
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>